ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 144

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

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ATtiny261A/461A/861A
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low. See
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry,
as shown in
Figure 15-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. See
When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set.
In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC
again, and a new conversion will be initiated on the first rising ADC clock edge.
Figure 15-5. ADC Timing Diagram, Single Conversion
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Figure 15-4
1
1
2
MUX and REFS
Update
2
MUX and REFS
Update
below.
12
3
13
Sample & Hold
Figure
4
14
5
15
15-3.
6
Sample & Hold
16
First Conversion
17
7
One Conversion
18
8
19
9
20
10
Conversion
Complete
21
11
22
Conversion
Complete
12
23
24
13
Figure
25
Sign and MSB of Result
Sign and MSB of Result
LSB of Result
Next Conversion
1
15-5.
Next
Conversion
1
LSB of Result
8197B–AVR–01/10
2
MUX and REFS
Update
2
MUX and REFS
Update
3
3