ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 148

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

15.9
15.10 ADC Accuracy Definitions
148
Noise Canceling Techniques
ATtiny261A/461A/861A
Figure 15-8. Analog Input Circuitry
The capacitor in
and any stray or parasitic capacitance inside the device. The value given is worst case.
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher imped-
ance is used, the sampling time will depend on how long the source needs to charge the S/H
capacitor, with can vary widely. The user is recommended to minmimize the charge transfer time
by using low impedant sources, only, with slowly varying signals.
Signal components higher than the Nyquist frequency (f
distortion from unpredictable signal convolution. The user is advised to remove high frequency
components with a low-pass filter before applying the signals as inputs to the ADC.
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. When conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as
described in
is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as
described in
bypass capacitors does reduce the need for using ADC Noise Reduction Mode
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior:
• Keep analog signal paths as short as possible.
• Make sure analog tracks run over the analog ground plane.
• Keep analog tracks well away from high-speed switching digital tracks.
• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.
• Place bypass capacitors as close to V
ADCn
Section 15.7 on page
Section 15.12 on page
Figure 15-8
depicts the total capacitance, including the sample/hold capacitor
I
IH
147. This is especially the case when system clock frequency
I
IL
152. A good system design with properly placed, external
CC
and GND pins as possible.
1..100 kΩ
ADC
/2) should not be present to avoid
C
S/H
= 14 pF
n
-1.
V
CC
REF
/2
8197B–AVR–01/10
in 2
n
steps