ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 91

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

12.3.1.1
12.3.1.2
12.4
8197B–AVR–01/10
Counter Unit
Prescaler Reset
Prescaler Initialization for Asynchronous Mode
Setting the PSR1 bit in TCCR1B register resets the prescaler. It is possible to use the Prescaler
Reset for synchronizing the Timer/Counter to program execution.
To change Timer/Counter1 to the asynchronous mode follow the procedure below:
The main part of the Timer/Counter1 is the programmable bi-directional counter unit.
4
Figure 12-4. Counter Unit Block Diagram
Signal description (internal signals):
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
asynchronous PLL clock using the Clock Select bits (CS13:0) and the PCK Enable bit (PCKE).
When no clock source is selected (CS13:0 = 0) the timer is stopped. However, the TCNT1 value
can be accessed by the CPU, regardless of whether clk
rides (has priority over) all counter clear or count operations.
The counting sequence of the Timer/Counter1 is determined by bits WGM11:10, PWM1A and
PWM1B, located in the Timer/Counter1 Control Registers (TCCR1A, TCCR1C and TCCR1D).
For more details about advanced counting sequences and waveform generation, see
Operation” on page
of operation and can be used for generating a CPU interrupt.
shows a block diagram of the counter and its surroundings.
1. Enable PLL.
2. Wait 100 µs for PLL to stabilize.
3. Poll the PLOCK bit until it is set.
4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode.
count
direction
clear
clk
top
bottom
Tn
DATA BUS
TCNT1
97. The Timer/Counter Overflow Flag (TOV1) is set according to the mode
T1
). The timer clock is generated from an synchronous system clock or an
TCNT1 increment or decrement enable.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
direction
count
clk
clear
T1
bottom
Control Logic
T1
top
is present or not. A CPU write over-
TOV1
T1
PCKE
PCK
CK
Timer/Counter1 Count Enable
( From Prescaler )
in the following.
Figure 12-
“Modes of
91