ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 133

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

8197B–AVR–01/10
Table 13-1.
Note:
• Bit 3:2 – USICS1:0: Clock Source Select
These bits set the clock source for the USI Data Registerr and counter. The data output latch
ensures that the output is changed at the opposite edge of the sampling of the data input
(DI/SDA) when using external clock source (USCK/SCL). When software strobe or
Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and
therefore the output is changed immediately. Clearing the USICS1:0 bits enables software
strobe option. When using this option, writing a one to the USICLK bit clocks both the USI Data
Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer
used as a strobe, but selects between external clocking and software clocking by the USITC
strobe bit.
Table 13-2 on page 133
clock source used for the USI Data Register and the 4-bit counter.
Table 13-2.
USIWM1
USICS1
1
1
0
0
0
1
1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively
to avoid confusion between the modes of operation.
USIWM0
USICS0
Relationship between USIWM1:0 and USI Operation (Continued)
Relations between the USICS1:0 and USICLK Setting
0
1
0
0
1
0
Description
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and
use open-collector output drives. The output drivers are enabled by setting the
corresponding bit for SDA and SCL in the DDRA register.
When the output driver is enabled for the SDA pin, the output driver will force
the line SDA low if the output of the
bit in the PORTA register is zero. Otherwise, the SDA line will not be driven (i.e.,
it is released). When the SCL pin output driver is enabled the SCL line will be
forced low if the corresponding bit in the PORTA register is zero, or by the start
detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and the
output is enabled. Clearing the Start Condition Flag (USISIF) releases the line.
The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on
the SDA and SCL port pin are disabled in Two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
Same operation as in two-wire mode above, except that the SCL line is also
held low when a counter overflow occurs, and until the Counter Overflow Flag
(USIOIF) is cleared.
USICLK
shows the relationship between the USICS1:0 and USICLK setting and
X
0
1
0
USI Data Register Clock
Source
No Clock
Software clock strobe
(USICLK)
Timer/Counter0 Compare
Match
External, positive edge
USI Data Register
4-bit Counter Clock Source
No Clock
Software clock strobe
(USICLK)
Timer/Counter0 Compare
Match
External, both edges
(1)
.
or the corresponding
133