ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 82

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

11.10 Register Description
11.10.1
82
ATtiny261A/461A/861A
TCCR0A – Timer/Counter0 Control Register A
• Bit 7– TCW0: Timer/Counter0 Width
When this bit is written to one 16-bit mode is selected as described
Timer/Counter0 width is set to 16-bits and the Output Compare Registers OCR0A and OCR0B
are combined to form one 16-bit Output Compare Register. Because the 16-bit registers
TCNT0H/L and OCR0B/A are accessed by the AVR CPU via the 8-bit data bus, special proce-
dures must be followed. These procedures are described in section
bit Mode” on page
• Bit 6– ICEN0: Input Capture Mode Enable
When this bit is written to onem, the Input Capture Mode is enabled.
• Bit 5 – ICNC0: Input Capture Noise Canceler
Setting this bit activates the Input Capture Noise Canceler. When the noise canceler is acti-
vated, the input from the Input Capture Pin (ICP0) is filtered. The filter function requires four
successive equal valued samples of the ICP0 pin for changing its output. The Input Capture is
therefore delayed by four System Clock cycles when the noise canceler is enabled.
• Bit 4 – ICES0: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICP0) that is used to trigger a capture
event. When the ICES0 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES0 bit is written to one, a rising (positive) edge will trigger the capture. When a cap-
ture is triggered according to the ICES0 setting, the counter value is copied into the Input
Capture Register. The event will also set the Input Capture Flag (ICF0), and this can be used to
cause an Input Capture Interrupt, if this interrupt is enabled.
• Bit 3 - ACIC0: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter0 to be trig-
gered by the Analog Comparator. The comparator output is in this case directly connected to the
input capture front-end logic, making the comparator utilize the noise canceler and edge select
features of the Timer/Counter0 Input Capture interrupt. When written logic zero, no connection
between the Analog Comparator and the input capture function exists. To make the comparator
trigger the Timer/Counter0 Input Capture interrupt, the TICIE0 bit in the Timer Interrupt Mask
Register (TIMSK) must be set.
• Bits 2:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – CTC0: Waveform Generation Mode
This bit controls the counting sequence of the counter, the source for maximum (TOP) counter
value, see
Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see
ation” on page
Bit
0x15 (0x35)
Read/Write
Initial Value
Figure 11-7 on page
75).
TCW0
R/W
7
0
78.
ICEN0
R/W
6
0
77. Modes of operation supported by the Timer/Counter unit are:
ICNC0
R/W
5
0
ICES0
R/W
4
0
ACIC0
R/W
3
0
R
2
0
–
“Accessing Registers in 16-
Figure 11-7 on page
R
1
–
0
“Modes of Oper-
CTC0
R/W
0
0
8197B–AVR–01/10
TCCR0A
77.