ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 121
ATTINY861A-SU
Manufacturer Part Number
ATTINY861A-SU
Description
IC, MCU, 8BIT, 8K FLASH, 20SOIC
Manufacturer
Atmel
Datasheet
1.ATTINY461A-MU.pdf
(292 pages)
Specifications of ATTINY861A-SU
Controller Family/series
ATtiny
No. Of I/o's
16
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
No.
RoHS Compliant
Core Size
8bit
Program Memory Size
8KB
Oscillator Type
External, Internal
Rohs Compliant
Yes
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12.12.13 TIMSK – Timer/Counter1 Interrupt Mask Register
12.12.14 TIFR – Timer/Counter1 Interrupt Flag Register
8197B–AVR–01/10
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the
internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are
described in section
• Bit 7- OCIE1D: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1D bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare MatchD, interrupt is enabled. The corresponding interrupt at vector
$010 is executed if a compare matchD occurs. The Compare Flag in Timer/Counter1 is set (one)
in the Timer/Counter Interrupt Flag Register.
• Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector
$003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one)
in the Timer/Counter Interrupt Flag Register.
• Bit 5 - OCIE1B: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector
$009 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one)
in the Timer/Counter Interrupt Flag Register.
• Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is
executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the
Timer/Counter Interrupt Flag Register - TIFR.
• Bit 7- OCF1D: Output Compare Flag 1D
The OCF1D bit is set (one) when compare match occurs between Timer/Counter1 and the data
value in OCR1D - Output Compare Register 1D. OCF1D is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF1D is cleared, after synchroniza-
tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1D, and OCF1D
are set (one), the Timer/Counter1 D compare match interrupt is executed.
• Bit 6 - OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data
value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing
Bit
0x39 (0x59)
Read/Write
Initial value
Bit
0x38 (0x58)
Read/Write
Initial value
OCIE1D
OCF1D
R/W
R/W
7
0
7
0
“Accessing 10-Bit Registers” on page
OCIE1A
OCF1A
R/W
R/W
6
0
6
0
OCIE1B
OCF1B
R/W
R/W
5
0
5
0
OCIE0A
OCF0A
R/W
R/W
4
0
4
0
OCIE0B
OCF0B
R/W
R/W
3
0
3
0
106.
TOIE1
TOV1
R/W
R/W
2
0
2
0
TOIE0
TOV0
R/W
R/W
1
0
1
0
TICIE0
ICF0
R/W
R/W
0
0
0
0
TIMSK
TIFR
121
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