ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 129

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

13.3.5
13.3.6
13.4
8197B–AVR–01/10
Alternative USI Usage
Start Condition Detector
Clock speed considerations
If the slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the master does a read operation it must terminate the operation by forcing the
acknowledge bit low after the last byte transmitted.
The start condition detector is shown in
to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled
in Two-wire mode.
Figure 13-6. Start Condition Detector, Logic Diagram
The start condition detector works asynchronously and can therefore wake up the processor
from power-down sleep mode. However, the protocol used might have restrictions on the SCL
hold time. Therefore, when using this feature in this case the Oscillator start-up time set by the
CKSEL Fuses (see
to the USISIF bit description on page 131 for further details.
Maximum frequency for SCL and SCK is f
receive rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock Con-
trol Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the
actual data rate in two-wire mode.
The flexible design of the USI allows it to be used for other tasks when serial communication is
not needed. Below are some examples.
3. The master set the first bit to be transferred and releases the SCL line (C). The slave
4. After eight bits containing slave address and data direction (read or write) have been
5. When the slave is addressed, it holds the SDA line low during the acknowledgment
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is
samples the data and shifts it into the USI Data Register at the positive edge of the SCL
clock.
transferred, the slave counter overflows and the SCL line is forced low (D). If the slave
is not the one the master has addressed, it releases the SCL line and waits for a new
start condition.
cycle before holding the SCL line low again (i.e., the USI Counter Register must be set
to 14 before releasing SCL at (D)). Depending on the R/W bit the master or slave
enables its output. If the bit is set, a master read operation is in progress (i.e., the slave
drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).
given by the master (F), or a new start condition is given.
Write( USISIF)
“Clock System” on page
SDA
SCL
Figure
CK
24) must also be taken into the consideration. Refer
/ 2. This is also the maximum data transmit and
13-6. The SDA line is delayed (in the range of 50
D Q
CLR
D Q
CLR
USISIF
CLOCK
HOLD
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