ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 120

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

12.12.10 OCR1B – Timer/Counter1 Output Compare Register B
12.12.11 OCR1C – Timer/Counter1 Output Compare Register C
12.12.12 OCR1D – Timer/Counter1 Output Compare Register D
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ATtiny261A/461A/861A
The output compare register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does
only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and
OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-
ing the compare event.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the
internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are
described in section
The output compare register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1, and a compare match will clear TCNT1. This register has the same function in
Normal mode and PWM modes.
Note that, if a smaller value than three is written to the Output Compare Register C, the value is
automatically replaced by three as it is a minumum value allowed to be written to this register.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the
internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are
described in section
The output compare register D is an 8-bit read/write register.
The Timer/Counter Output Compare Register D contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does
only occur if Timer/Counter1 counts to the OCR1D value. A software write that sets TCNT1 and
OCR1D to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1D after a synchronization delay follow-
ing the compare event.
Bit
0x2C (0x4C)
Read/Write
Initial value
Bit
0x2B (0x4B)
Read/Write
Initial value
Bit
0x2A (0x4A)
Read/Write
Initial value
MSB
MSB
MSB
R/W
R/W
R/W
7
0
7
1
7
0
“Accessing 10-Bit Registers” on page
“Accessing 10-Bit Registers” on page
R/W
R/W
R/W
6
0
6
1
6
0
R/W
R/W
R/W
5
0
5
1
5
0
R/W
R/W
R/W
4
0
4
1
4
0
R/W
R/W
R/W
3
0
3
1
3
0
106.
106.
R/W
R/W
R/W
2
0
2
1
2
0
R/W
R/W
R/W
1
0
1
1
1
0
LSB
R/W
LSB
R/W
LSB
R/W
0
0
0
1
0
0
8197B–AVR–01/10
OCR1D
OCR1B
OCR1C