ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 131

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

13.5.2
13.5.3
8197B–AVR–01/10
USIBR – USI Buffer Register
USISR – USI Status Register
The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is com-
pleted, and instead of accessing the USI Data Register (the Serial Register) the USI Data Buffer
can be accessed when the CPU reads the received data. This gives the CPU time to handle
other program tasks too as the controlling of the USI is not so timing critical. The USI flags as set
same as when reading the USIDR register.
The Status Register contains Interrupt Flags, line Status Flags and the counter value.
• Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is
detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 &
USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global
Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF
bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.
A start condition interrupt will wakeup the processor from all sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An
interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global
Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit.
Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected.
The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is
useful when implementing Two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The
flag is only valid when Two-wire mode is used. This signal is useful when implementing Two-
wire bus master arbitration.
• Bits 3:0 – USICNT3:0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or
written by the CPU.
Bit
0x10 (0x30)
Read/Write
Initial Value
Bit
0x0E (0x2E)
Read/Write
Initial Value
R/W
7
USISIF
0
7
MSB
R
0
6
USIOIF
R/W
0
6
R
0
5
USIPF
R/W
0
5
R
0
4
USIDC
R
0
4
R
0
3
USICNT3
R/W
0
3
R
0
2
USICNT2
R/W
0
2
R
0
1
USICNT1
R/W
0
1
R
0
0
USICNT0
R/W
0
0
LSB
R
0
USIBR
USISR
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