UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 131

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

5.6.3 Example of controlling subsystem clock
The following describes examples of setting procedures for the following cases.
(1) When oscillating XT1 clock
(2) When using subsystem clock as CPU clock
(3) When stopping subsystem clock
(3) Example of setting procedure when stopping the internal high-speed oscillation clock
The following two types of subsystem clocks are available.
When the subsystem clock is not used, the XT1/P123 and XT2/P124 pins can be used as Input port pins.
Caution The XT1/P123 and XT2/P124 pins are in the Input port mode after a reset release.
XT1 clock:
The internal high-speed oscillation clock can be stopped in the following two ways.
(a) To execute a STOP instruction
(b) To stop internal high-speed oscillation clock by setting RSTOP to 1
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition, stop
Executing the STOP instruction to set the STOP mode
Setting RSTOP to 1 and stopping the internal high-speed oscillation clock
<1> Setting of peripheral hardware
<2> Setting the X1 clock oscillation stabilization time after standby release
<3> Executing the STOP instruction
<1> Confirming the CPU clock status (PCC and MCM registers)
<2> Stopping the internal high-speed oscillation clock (RCM register)
CLS
0
0
1
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 19 STANDBY FUNCTION).
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed.
When the STOP instruction is executed, the system is placed in the STOP mode and internal high-
speed oscillation clock is stopped.
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so
change the CPU clock to the high-speed system clock or subsystem clock.
When RSTOP is set to 1, internal high-speed oscillation clock is stopped.
peripheral hardware that is operating on the internal high-speed oscillation clock.
MCS
0
1
×
Crystal/ceramic resonator is connected across the XT1 and XT2 pins.
Internal high-speed oscillation clock
High-speed system clock
Subsystem clock
CHAPTER 5 CLOCK GENERATOR
User’s Manual U18698EJ1V0UD
CPU Clock Status
131