UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 327

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

1. Stop bit length: 1
2. Stop bit length: 2
(c) Transmission
If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6
(TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit
data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to
the data.
When transmission is started, the start bit is output from the T
followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity
and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is
generated.
Transmission is stopped until the data to be transmitted next is written to TXS0.
Figure 13-9 shows the timing of the transmission completion interrupt request (INTST0). This interrupt
occurs as soon as the last stop bit has been output.
Caution After transmit data is written to TXS0, do not write the next transmit data before the
T
T
X
X
D0 (output)
D0 (output)
INTST0
INTST0
transmission completion interrupt signal (INTST0) is generated.
Figure 13-9. Transmission Completion Interrupt Request Timing
Start
Start
CHAPTER 13 SERIAL INTERFACE UART0
D0
D0
User’s Manual U18698EJ1V0UD
D1
D1
D2
D2
D6
D6
X
D0 pin, and the transmit data is output
D7
D7
Parity
Parity
Stop
Stop
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