UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 64

8BIT UC, 32K FLASH, 1KB RAM, LCD

UPD78F0413GA-GAM-AX

Manufacturer Part Number
UPD78F0413GA-GAM-AX
Description
8BIT UC, 32K FLASH, 1KB RAM, LCD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0413GA-GAM-AX

Controller Family/series
UPD78F
No. Of I/o's
30
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
32KB
Oscillator Type
External, Internal

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3.3 Instruction Address Addressing
each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction
is executed. When a branch instruction is executed, the branch destination information is set to PC and branched by
the following addressing (for details of instructions, refer to the 78K/0 Series Instructions User’s Manual (U12326E)).
3.3.1 Relative addressing
64
An instruction address is determined by contents of the program counter (PC), and is normally incremented (+1 for
[Function]
[Illustration]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched.
displacement value is treated as signed two’s complement data ( 128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the 128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
PC
When S = 0, all bits of
When S = 1, all bits of
15
15
15
are 0.
are 1.
8
PC
+
CHAPTER 3 CPU ARCHITECTURE
7
S
User’s Manual U18698EJ1V0UD
6
jdisp8
0
0
0
...
PC indicates the start address
of the instruction after the BR instruction.
The

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