UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 249

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

8.4.2 Operation as PWM output
register during timer operation is prohibited.
register during timer operation is possible.
counter Hn and the CMP0n register match after the timer count is started. PWM output (TOHn output) outputs an
inactive level when 8-bit timer counter Hn and the CMP1n register match.
no pins for external output are available.
TMHMDn
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n
The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n
The operation in PWM output mode is as follows.
PWM output (TOHn output) outputs an active level and 8-bit timer counter Hn is cleared to 0 when 8-bit timer
The timer output of TMH2 (PWM output) can only be used as an external event input enable signal of TM52. Note,
<1> Set each register.
<2> The count operation starts when TMHEn = 1.
<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled.
Setting
(i) Setting timer H mode register n (TMHMDn)
(ii) Setting CMP0n register
(iii) Setting CMP1n register
When the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is
cleared, an interrupt request signal (INTTMHn) is generated, an active level is output. At the same time, the
compare register to be compared with the 8-bit timer counter Hn is changed from the CMP0n register to the
CMP1n register.
TMHEn
0
Remarks 1. n = 0 to 2, however, TOH0 and TOH1 only for TOHn
Compare value (N): Cycle setting
Compare value (M): Duty setting
CKSn2
0/1
2. 00H
CKSn1
Figure 8-13. Register Setting in PWM Output Mode
0/1
CMP1n (M) < CMP0n (N)
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
CKSn0
0/1
User’s Manual U18698EJ1V0UD
TMMDn1
1
TMMDn0 TOLEVn
0
FFH
0/1
TOENn
1
Timer output enabled
Default setting of timer output level
PWM output mode selection
Count clock (f
Count operation stopped
CNT
) selection
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