UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 249
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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(7) Operation of OVF0n flag
(8) One-shot pulse output
(a) Setting OVF0n flag (1)
(b) Clearing OVF0n flag
One-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the
TI00n pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match
between TM0n and CR00n.
Remark n = 0:
The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows.
Select the clear & start mode entered upon a match between TM0n and CR00n.
Set CR00n to FFFFH.
When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H
Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count clock is counted
(before the value of TM0n becomes 0001H), it is set to 1 again and clearing is invalid.
n = 0, 1:
↓
↓
µ
µ
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Count pulse
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
INTTM00n
OVF0n
CR00n
TM0n
Figure 7-62. Operation Timing of OVF0n Flag
FFFEH
FFFFH
User’s Manual U17260EJ6V0UD
FFFFH
0000H
0001H
249
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