GS1559CBE2 GENNUM, GS1559CBE2 Datasheet
GS1559CBE2
Specifications of GS1559CBE2
Related parts for GS1559CBE2
GS1559CBE2 Summary of contents
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... TRS ID words, line-based CRC words, ancillary data checksum words, EDH CRC words, and line numbers. Illegal code re-mapping is also available. All processing functions may be individually enabled or disabled via host interface control. *For new designs use GO1555 May 2007 GS1559 HD-LINX™ II GS1559 Data Sheet www.gennum.com ...
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Functional Block Diagram CD1 carrier_detect CD2 TERM 1 DDI_1 DDI_1 Reclocker TERM 2 DDI_2 DDI_2 (o/p mute) rclk_bypass pll_lock SDO_EN/DIS SDO SDO RSET rclk_ctrl LOCK detect pll_lock SMPTE De- scramble, Word alignment and flywheel S->P K28.5 sync detect, DVB-ASI word ...
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Contents Key Features .................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 Functional Block Diagram .............................................................................................2 1. Pin Out .....................................................................................................................5 1.1 Pin Assignment ...............................................................................................5 1.2 Pin Descriptions ..............................................................................................6 2. Electrical Characteristics ........................................................................................16 2.1 Absolute Maximum Ratings ..........................................................................16 2.2 DC Electrical Characteristics ........................................................................16 2.3 AC Electrical ...
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DVB-ASI 8b/10b Decoding and Word Alignment................................41 4.8.2 Status Signal Outputs .........................................................................41 4.9 Data Through Mode ......................................................................................42 4.10 Additional Processing Functions.................................................................42 4.10.1 FIFO Load Pulse...............................................................................42 4.10.2 Ancillary Data Detection and Indication ............................................43 4.10.3 SMPTE 352M Payload Identifier.......................................................46 4.10.4 Automatic Video ...
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Pin Out 1.1 Pin Assignment VCO_ VCO_ A LF VCO GND VCC LB_ B CP_VDD CP_GND CP_CAP CONT BUFF PD_VDD PD/BUFF C NC _VDD _GND D NC IP_SEL DDI1 TERM1 SD/HD DDI1 ...
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Pin Descriptions Table 1-1: Pin Descriptions Pin Name Number VCO_VCC A3 VCO_GND A4, A5 VCO, VCO A6, B5, NC B6, C4, C5, D2, D3, D7, E3, E7, F2, F3, F7, G2, G3, G7, H3, J2, J3, ...
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Table 1-1: Pin Descriptions (Continued) Pin Name Number A10, A9, DOUT[19:10] Synchronous B10, B9, C10, C9, D10, D9, E10 CP_CAP B2 CP_VDD B3 CP_GND B4 LB_CONT Timing Type Description Output PARALLEL DATA BUS with PCLK Signal levels are ...
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Table 1-1: Pin Descriptions (Continued) Pin Name Number B7 FW_EN/DIS Synchronous B8, F8, J8 IO_GND C1 BUFF_VDD C2 PD_VDD C3 PDBUFF_GND C6 MASTER/SLAVE Synchronous C7 RC_BYP Synchronous Timing Type Description Non Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. ...
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Table 1-1: Pin Descriptions (Continued) Pin Name Number C8 YANC Synchronous D1, E1 DDI1, DDI1 D4 IP_SEL Synchronous D5 DVB_ASI Synchronous D6 LOCKED Synchronous Timing Type Description Output STATUS SIGNAL OUTPUT with PCLK Signal levels are LVCMOS/LVTTL compatible. Used to ...
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... STATUS SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of a serial digital input signal. Normally generated by a Gennum automatic cable equalizer. When LOW, the serial digital input signal received at the DDI1 and DDI1 pins is considered valid. When HIGH, the associated serial digital input signal is considered to be invalid ...
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Table 1-1: Pin Descriptions (Continued) Pin Name Number F4 20bit/10bit Synchronous F10, F9, DOUT[9:0] Synchronous G10, G9, H10, H9, J10, J9, K10, K9 G1, H1 DDI2, DDI2 Timing Type Description Non Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. ...
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Table 1-1: Pin Descriptions (Continued) Pin Name Number G4 IOPROC_EN/DIS Synchronous G5 SMPTE_BYPASS Synchronous G6 RESET_TRST Synchronous Timing Type Description Non Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable I/O processing features. When set ...
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Table 1-1: Pin Descriptions (Continued) Pin Name Number G8 FIFO_LD Synchronous H2 TERM2 H4 CS_TMS Synchronous H5 SCLK_TCK Synchronous H6 SDOUT_TDO Synchronous H7 DATA_ERROR Synchronous Timing Type Description Output CONTROL SIGNAL OUTPUT with PCLK Signal levels are LVCMOS/LVTTL compatible. Used ...
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... STATUS SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of a serial digital input signal. Normally generated by a Gennum automatic cable equalizer. When LOW, the serial digital input signal received at the DDI2 and DDI2 pins is considered valid. When HIGH, the associated serial digital input signal is considered to be invalid ...
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Table 1-1: Pin Descriptions (Continued) Pin Name Number K2 CD_VDD K3, K4 SDO, SDO K5 CD_GND K6 JTAG/HOST Synchronous K7 F Synchronous Timing Type Description – Power Power supply connection for the serial digital cable driver. Connect to +1.8V DC ...
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Electrical Characteristics 2.1 Absolute Maximum Ratings 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics T = 0°C to 70°C, unless otherwise specified. A Parameter Symbol System Operation Temperature Range T A Digital Core Supply Voltage CORE_VDD Digital I/O ...
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Table 2-1: DC Electrical Characteristics (Continued 0°C to 70°C, unless otherwise specified. A Parameter Symbol Total Device Power Digital I/O Input Logic LOW V IL Input Logic HIGH V IH Output Logic LOW V ...
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AC Electrical Characteristics Table 2-2: AC Electrical Characteristics T = 0°C to 70°C, unless otherwise shown A Parameter Symbol System Serial Digital Input IJT Jitter Tolerance Master Mode Asynchronous Lock Time Slave Mode Asynchronous Lock Time Device Latency Reset ...
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Table 2-2: AC Electrical Characteristics (Continued 0°C to 70°C, unless otherwise shown A Parameter Symbol Serial Output Intrinsic t IJ Jitter Parallel Output Parallel Clock f PCLK Frequency Parallel Clock Duty DC PCLK Cycle Output Data Hold t ...
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Solder Reflow Profiles The GS1559 is available Pb-free package recommended that the Pb package be soldered with Pb paste using the Standard Eutectic profile shown in Figure 2-1, and the Pb-free package be ...
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Input/Output Circuits All resistors in ohms, all capacitors in farads, unless otherwise shown. DDI VDD 50 45K TERM 150K 50 DDI Figure 3-1: Serial Digital Input VCO VDD 25 1. VCO Figure 3-2: VCO Input 7.2K 865mV ...
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Figure 3-4: Serial Digital Output LF CP_CAP 300 Figure 3-5: VCO Control Output & PLL Lock Time Capacitor 30572 - 7 May 2007 GS1559 Data Sheet SDO SDO ...
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... TERM1 and TERM2 pins. The input common mode level is set by internal biasing resistors such that the serial digital input signals must be AC coupled into the device. Gennum recommends using a capacitor value of 4.7uF to accommodate pathological signals. The input buffers use a separate power supply of +1.8V DC supplied via the BUFF_VDD and PDBUFF_GND pins ...
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... When IP_SEL is set LOW, serial digital input 2 (DDI2 / DDI2) is selected. For each of the differential inputs, an associated carrier detect input signal is included, (CD1 and CD2). These signals are generated by Gennum's family of automatic cable equalizers. When LOW, CDx indicates that a valid serial digital data stream is being delivered to the GS1559 by the equalizer ...
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... When not using the serial digital output from the GS1559, the SDO and SDO pins should be left unconnected (floating). In addition, the SDO_EN pin should be set LOW and the RSET pin may be AC terminated to analog ground through a 10nF capacitor. Gennum recommends using the GS1528A SDI Dual Slew-Rate Cable Driver to meet SMPTE specifications. 30572 - 7 May 2007 GS1559 Data Sheet 68 ...
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Output Swing 4.4.2 Reclocker Bypass Control Nominally, the voltage swing of the serial digital loop-through output is 800mV single-ended into a 75Ω load. This is set externally by connecting the RSET pin to CD_VDD through 281Ω. The loop-through output ...
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Serial Digital Output Mute 4.5 Serial-To-Parallel Conversion The GS1559 will automatically mute the serial digital loop-through output in both master and slave modes when the internal carrier_detect signal indicates an invalid serial input. The loop-through output will also be ...
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Modes Of Operation 4.6.1 Lock Detect The GS1559 has two basic modes of operation which determine how the lock detect block controls the integrated reclocker. Master mode is enabled when the application layer sets the MASTER/SLAVE pin HIGH, and ...
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Master Mode 4.6.3 Slave Mode For SMPTE and DVB-ASI inputs, the lock detect block will only assert the LOCKED output signal HIGH if (1) the reclocker has locked to the input data stream as indicated by the internal pll_lock ...
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Table 4-2: Master Mode Output Status Signals FORMAT SMPTE_BYPASS HD SMPTE HIGH SD SMPTE HIGH DVB-ASI LOW NOT SMPTE OR LOW DVB-ASI* *NOTE: When the device locks to the data stream in PLL lock mode, the parallel outputs will be ...
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SMPTE Functionality 4.7.1 SMPTE Descrambling and Word Alignment 4.7.2 Internal Flywheel The GS1559 is said SMPTE mode once the device has detected SMPTE TRS sync words and locked to the input data stream as described in ...
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Switch Line Lock Handling The flywheel 'learns' the video standard by timing the horizontal and vertical reference information contained in the TRS ID words of the received video stream. Full synchronization of the flywheel to the received video standard ...
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Video source 1 EAV ANC SAV ACTIVE PICTURE Video source 2 EAV ANC SAV ACTIVE PICTURE DATA IN EAV ANC SAV ACTIVE PICTURE DATA OUT EAV ANC SAV ACTIVE PICTURE Flywheel TRS position FW_EN/DIS Video source 1 EAV ANC SAV ...
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Table 4-4: Switch Line Position for Digital Systems System Video Format HD-SDTI 1920x1080 (PsF) 1920x1080 (2:1) 1280x720 (1:1) SDTI 720x576/50 (2:1) 720x483/59.94 (2:1) 750 1280x720/60 (1:1) 1280x720/50 (1:1) 1280x720/30 (1:1) 1280x720/25 (1:1) 1280x720/24 (1:1) 1125 1920x1080/30 (PsF) 1920x1080/25 (PsF) 1920x1080/24 ...
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Table 4-4: Switch Line Position for Digital Systems (Continued) System Video Format 525 960x483/59.94 (2:1) 960x483/59.94 (2:1) 720x483/59.94 (2:1) 720x483/59.94 (2:1) 720x483/59.94 (2:1) 720x483/59.94 (2:1) 720x483/59.94 (2:1) 720x483/59.94 (2:1) 720x483/59.94 (1:1) 720x483/59.94 (1:1) 720x483/59.94 (1:1) 720x483/59.94 (1:1) 720x483/59.94 (1:1) 625 ...
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HVF Timing Signal Generation The GS1559 extracts critical timing parameters from either the received TRS signals (FW_EN/DIS = LOW), or from the internal flywheel-timing generator (FW_EN/DIS = HIGH). Horizontal blanking period (H), vertical blanking period (V), and even / ...
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PCLK 3FF 000 LUMA DATA OUT 3FF 000 CHROMA DATA OUT PCLK MULTIPLEXED 3FF Y/Cr/Cb DATA OUT PCLK MULTIPLEXED 3FF Y/Cr/Cb DATA OUT PCLK 3FF CHROMA DATA OUT LUMA DATA OUT ...
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DVB-ASI Functionality 4.8.1 DVB-ASI 8b/10b Decoding and Word Alignment 4.8.2 Status Signal Outputs The GS1559 is said DVB-ASI mode once the device has detected 32 consecutive DVB-ASI words without a single word or disparity error being ...
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DDI DDI 4.9 Data Through Mode 4.10 Additional Processing Functions 4.10.1 FIFO Load Pulse GS1559 Figure 4-4: DVB-ASI FIFO Implementation Using The GS1559 The GS1559 may be configured by the application layer to operate as a simple serial-to-parallel converter. In ...
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LUMA DATA OUT CHROMA DATA OUT FIFO_LD PCLK MULTIPLEXED 3FF Y/Cr/Cb DATA OUT FIFO_LD CHROMA DATA OUT PCLK MULTIPLEXED Y/Cr/Cb DATA OUT FIFO_LD 4.10.2 Ancillary Data Detection and Indication PCLK 3FF 000 000 3FF FIFO LOAD PULSE - HD 20BIT ...
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In SD mode, (SD/HD = HIGH), the YANC and CANC signal operation will depend on the output data format. For 20-bit demultiplexed data, (see Outputs on page However, for 10-bit multiplexed data, the YANC and CANC signals will both be ...
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Programmable Ancillary Data Detection Table 4-5: Host Interface Description for Programmable Ancillary Data Type Registers Register Name Bit Name ANC_TYPE1 15-8 ANC_TYPE1[15:8] Address: 005h 7-0 ANC_TYPE1[7:0] ANC_TYPE2 15-8 ANC_TYPE2[15:8] Address: 006h 7-0 ANC_TYPE2[7:0] ANC_TYPE3 15-8 ANC_TYPE3[15:8] Address: 007h 7-0 ...
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Table 4-5: Host Interface Description for Programmable Ancillary Data Type Registers (Continued) Register Name Bit Name ANC_TYPE4 15-8 ANC_TYPE4[15:8] Address: 008h 7-0 ANC_TYPE4[7:0] ANC_TYPE5 15-8 ANC_TYPE5[15:8] Address: 009h 7-0 ANC_TYPE5[7:0] 4.10.3 SMPTE 352M Payload Identifier Description Used to program the ...
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Table 4-6: Host Interface Description for SMPTE 352M Payload Identifier Registers Register Name Bit VIDEO_FORMAT_OUT_B 15-8 Address: 00Dh 7-0 VIDEO_FORMAT_OUT_A 15-8 Address: 00Ch 7-0 4.10.4 Automatic Video Standard and Data Format Detection 4.10.4.1 Video Standard Indication Name Description SMPTE352M Data ...
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Table 4-7: Host Interface Description for Video Standard and Data Format Register Register Name Bit Name VIDEO_STANDARD 15 – Address: 004h 14-10 VD_STD[4:0] 9 INT_PROG 8 STD_LOCK 7-4 CDATA_FORMAT[3:0] 3-0 YDATA_FORMAT[3:0] Table 4-8: Host Interface Description for Raster Structure Registers ...
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Table 4-9: Supported Video Standards (Continued) VD_STD[4:0] SMPTE Standard 07h 296M (HD) 08h 296M (HD) 09h 296M (HD) 0Ah 274M (HD) 0Bh 274M (HD) 0Ch 274M (HD) 0Dh 274M (HD) 0Eh 274M (HD) 0Fh 274M (HD) 10h 274M (HD) 11h ...
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Data Format Indication The luma and chroma data format codes will be reported in the YDATA_FORMAT[3:0] and CDATA_FORMAT[3:0] bits of the VIDEO_STANDARD register when the device is operating in HD mode, (SD/HD = LOW DVB-ASI mode, ...
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Error Detection and Indication The GS1559 contains a number of error detection functions to enhance operation of the device when operating in SMPTE mode. These functions, (except lock error detection), will not be available in either DVB-ASI or Data-Through ...
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Table 4-11: Host Interface Description for Error Status Register Register Name Bit Name ERROR_STATUS 15-11 – Address: 001h 10 VD_STD_ERR 9 FF_CRC_ERR 8 AP_CRC_ERR 7 LOCK_ERR 6 CCS_ERR 5 YCS_ERR 4 CCRC_ERR 3 YCRC_ERR 2 LNUM_ERR 1 SAV_ERR 0 EAV_ERR ...
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Table 4-12: Host Interface Description for Error Mask Register Register Name Bit Name ERROR_MASK 15-11 – Address: 01Ah 10 VD_STD_ERR_MASK 9 FF_CRC_ERR_MASK 8 AP_CRC_ERR_MASK 7 LOCK_ERR_MASK 6 CCS_ERR_MASK 5 YCS_ERR_MASK 4 CCRC_ERR_MASK 3 YCRC_ERR_MASK 2 LNUM_ERR_MASK 1 SAV_ERR_MASK 0 EAV_ERR_MASK ...
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Table 4-13: Host Interface Description for EDH Calculation Range Registers Register Name Bit Name AP_LINE_START_F0 15-10 – Address: 012h 9-0 AP_LINE_START_F0[9:0] AP_LINE_END_F0 15-10 – Address: 013h 9-0 AP_LINE_END_F0[9:0] AP_LINE_START_F1 15-10 – Address: 014h 9-0 AP_LINE_START_F1[9:0] AP_LINE_END_F1 15-10 – Address: 015h ...
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Table 4-13: Host Interface Description for EDH Calculation Range Registers (Continued) Register Name Bit Name FF_LINE_START_F0 15-10 – Address: 016h 9-0 FF_LINE_START_F0[9:0] FF_LINE_END_F0 15-10 – Address: 017h 9-0 FF_LINE_END_F0[9:0] FF_LINE_START_F1 15-10 – Address: 018h 9-0 FF_LINE_START_F1[9:0] FF_LINE_END_F1 15-10 – Address: ...
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Line Based CRC Error Detection 4.10.5.6 HD Line Number Error Detection 4.10.5.7 TRS Error Detection 4.10.6 Error Correction and Insertion The GS1559 will calculate line based CRC words for HD video signals for both the Y and C data ...
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Table 4-14: Host Interface Description for Internal Processing Disable Register Register Name Bit Name IOPROC_DISABLE 15-9 – Address: 000h 8 H_CONFIG 7-6 – 5 ILLEGAL_REMAP 4 EDH_CRC_INS 3 ANC_CSUM_INS 2 CRC_INS 1 LNUM_INS 0 TRS_INS 4.10.6.1 Illegal Code Remapping 4.10.6.2 ...
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Ancillary Data Checksum Error Correction 4.10.6.4 Line Based CRC Correction 4.10.6.5 HD Line Number Error Correction 4.10.6.6 TRS Error Correction 4.10.7 EDH Flag Detection NOTE: Although the GS1559 will modify and insert EDH CRC words and EDH packet checksums, ...
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... EDH flags may be set, and the source is replaced by one without EDH packets, the EDH_FLAG register will not be cleared. NOTE 3: The GS1559 will detect EDH flags, but will not update the flags if an EDH CRC error is detected. Gennum's GS1532 Multi-Rate Serializer allows the host to individually set EDH flags. Description Not Used ...
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Parallel Data Outputs 4.11.1 Parallel Data Bus Buffers Data outputs leave the device on the rising edge of PCLK as shown in and Figure 4-8. The data may be scrambled or unscrambled, framed or unframed, and may be presented ...
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Parallel Output in SMPTE Mode 4.11.3 Parallel Output in DVB-ASI Mode 4.11.4 Parallel Output in Data-Through Mode SD MODE PCLK DOUT[19:0] DATA Control signal output Figure 4-8: SD PCLK to Data Timing When the device is operating in SMPTE ...
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Parallel Output Clock (PCLK) Table 4-16: Parallel Data Output Format Output Data Format DOUT [19:10] SMPTE MODE 20bit DEMULTIPLEXED SD LUMA 10bit MULTIPLEXED SD LUMA / CHROMA 20bit DEMULTIPLEXED HD LUMA 10bit MULTIPLEXED HD LUMA / CHROMA DVB-ASI MODE ...
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... R/W RSV RSV The GSPI, or Gennum Serial Peripheral Interface 4-wire interface provided to allow the host to enable additional features of the device and /or to provide additional status information through configuration registers in the GS1559. The GSPI comprises a serial data input signal SDIN, serial data output signal SDOUT, an active low chip select CS, and a burst clock SCLK ...
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MSB D15 D14 D13 4.12.2 Data Read and Write Timing t 0 SCLK input data t 3 setup time CS SDIN RSV R/W RSV RSV RSV RSV RSV RSV SDOUT SCLK input data t 3 setup ...
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Where status registers contain less than the full 16 bits of information however, two or more registers may be combined at a single logical address. Table 4-17: GS1559 internal registers Address Register Name 000h IOPROC_DISABLE 001h ERROR_STATUS 003h EDH_FLAG 004h ...
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... JTAG/HOST input signal, but some means for tri-stating the host must exist in order to use the interface at ATE. This is represented in Application HOST Tri-State In-circuit ATE probe Figure 4-15: System JTAG Please contact your Gennum representative to obtain the BSDL model for the GS1559. 30572 - 7 May 2007 GS1559 Data Sheet Figure 4-14. ...
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Device Power Up 4.15 Device Reset +1.8V +1.65V CORE_VDD RESET_TRST The GS1559 has a recommended power supply sequence. To ensure correct power up, power the CORE_VDD pins before the IO_VDD pins. Device pins may also be driven prior to ...
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Application Reference Design 5.1 Typical Application Circuit (Part A) SDI 6.2n 75 EQ_GND 75 EQ_GND NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted. EQ_VCC 10n 1 VEE_A EQ_GND 1u ...
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Typical Application Circuit (Part ...
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References & Relevant Standards SMPTE 125M Component video signal 4:2:2 – bit parallel interface SMPTE 260M 1125 / 60 high definition production system – digital representation and bit parallel interface SMPTE 267M Bit parallel digital interface – component video ...
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Package & Ordering Information 7.1 Package Dimensions 30572 - 7 May 2007 GS1559 Data Sheet ...
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Packaging Data 7.3 Ordering Information Parameter Package Type Package Drawing Reference Moisture Saturation Level Junction to Case Thermal Resistance, θ Junction to Air Thermal Resistance, θ j-a Psi Pb-free and RoHS compliant Part Number Package GS1559-CBE2 100-ball BGA GS1559-CB ...
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... Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement ...