GS1559CBE2 GENNUM, GS1559CBE2 Datasheet - Page 42

• Manufacturer Part Number: GS1559CBE2
• Description: IC, DES, 48.5MHZ 20BIT 1.485GBPS BGA-100
• Manufacturer: GENNUM

Specifications of GS1559CBE2

• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: BGA
• No. Of Pins: 100
• Termination Type: SMD
• Control Interface: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.9 Data Through Mode
4.10 Additional Processing Functions
4.10.1 FIFO Load Pulse
DDI
DDI
Figure 4-4: DVB-ASI FIFO Implementation Using The GS1559
The GS1559 may be configured by the application layer to operate as a simple
serial-to-parallel converter. In this mode, the device presents data to the output
data bus without performing any decoding, descrambling or word-alignment.
Data through mode is enabled only when the MASTER/SLAVE, SMPTE_BYPASS,
and DVB_ASI input pins are set LOW. Under these conditions, the lock detection
algorithm enters PLL lock mode, (see
device may reclock data not conforming to SMPTE or DVB-ASI streams. The
LOCKED pin will indicate analog lock.
When operating in master mode, the GS1559 will set the SMPTE_BYPASS and
DVB_ASI signals to logic LOW if presented with a data stream without SMPTE
TRS ID words or DVB-ASI sync words. The LOCKED and data bus outputs will be
forced LOW and the serial digital loop-through output will be a buffered version of
the input.
The GS1559 contains an additional data processing block which is available in
SMPTE mode only, (see
To aid in the application-specific implementation of auto-phasing and line
synchronization functions, the GS1559 will generate a FIFO load pulse to reset
line-based FIFO storage.
The FIFO_LD output pin will normally be HIGH but will go LOW for one PCLK
period, thereby generating a FIFO write reset signal.
The FIFO load pulse will be generated such that it is co-timed to the SAV XYZ code
word presented to the output data bus. This ensures that the next PCLK cycle will
correspond to the first active sample of the video line.
Figure 4-5
output video data.
30572 - 7
shows the timing relationship between the FIFO_LD signal and the
May 2007
GS1559
SMPTE Functionality on page
PCLK = 27MHz
AOUT ~ HOUT
WORDERR
SYNCOUT
Lock Detect on page
8
CLK_IN
WE
GS1559 Data Sheet
34).
FIFO
31), such that the
CLK_OUT
8
42 of 73
READ_CLK
<27MHz
TS
FE
FF
WORDERR