GS1559CBE2 GENNUM, GS1559CBE2 Datasheet - Page 8

• Manufacturer Part Number: GS1559CBE2
• Description: IC, DES, 48.5MHZ 20BIT 1.485GBPS BGA-100
• Manufacturer: GENNUM

Specifications of GS1559CBE2

• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: BGA
• No. Of Pins: 100
• Termination Type: SMD
• Control Interface: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1-1: Pin Descriptions (Continued)
Number
B8, F8, J8
Pin
B7
C1
C2
C3
C6
C7
MASTER/SLAVE
PDBUFF_GND
FW_EN/DIS
BUFF_VDD
PD_VDD
RC_BYP
IO_GND
Name
Synchronous
Synchronous
Synchronous
30572 - 7
Timing
Non
Non
Non
–
–
–
–
/Output
May 2007
Power
Power
Power
Power
Type
Input
Input
Input
Description
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the noise immune flywheel of the device.
When set HIGH, the internal flywheel is enabled. This flywheel is used in
the extraction and generation of TRS timing signals, in automatic video
standards detection, and in manual switch line lock handling.
When set LOW, the internal flywheel is disabled and TRS correction and
insertion is unavailable.
Ground connection for digital I/O buffers. Connect to digital GND.
Power supply connection for the serial digital input buffers. Connect to
+1.8V DC analog.
Power supply connection for the phase detector. Connect to +1.8V DC
analog.
Ground connection for the phase detector and serial digital input buffers.
Connect to analog GND.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to determine the input / output selection for the DVB_ASI, SD/HD,
RC_BYP and SMPTE_BYPASS pins.
When set HIGH, the GS1559 is set to operate in master mode where
DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS become status signal
output pins set by the device. In this mode, the GS1559 will automatically
detect, reclock, deserialize and process SD SMPTE, HD SMPTE, or
DVB-ASI input data.
When set LOW, the GS1559 is set to operate in slave mode where
DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS become control signal
input pins. In this mode, the application layer must set these external
device pins for the correct reception of either SMPTE or DVB-ASI data.
Slave mode also supports the reclocking and deserializing of data not
conforming to SMPTE or DVB-ASI streams.
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The RC_BYP signal will be HIGH only when the device has successfully
locked to a SMPTE or DVB-ASI compliant input data stream. In this case,
the serial digital loop-through output will be a reclocked version of the
input.
The RC_BYP signal will be LOW whenever the input does not conform to
a SMPTE or DVB-ASI compliant data stream. In this case, the serial digital
loop-through output will be a buffered version of the input.
Slave Mode (MASTER/SLAVE = LOW)
When set HIGH, the serial digital output will be a reclocked version of the
input signal regardless of whether the device is in SMPTE, DVB-ASI or
Data-Through mode.
When set LOW, the serial digital output will be a buffered version of the
input signal in all modes.
GS1559 Data Sheet
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