GS1559CBE2 GENNUM, GS1559CBE2 Datasheet - Page 31

• Manufacturer Part Number: GS1559CBE2
• Description: IC, DES, 48.5MHZ 20BIT 1.485GBPS BGA-100
• Manufacturer: GENNUM

Specifications of GS1559CBE2

• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: BGA
• No. Of Pins: 100
• Termination Type: SMD
• Control Interface: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.6 Modes Of Operation
4.6.1 Lock Detect
The GS1559 has two basic modes of operation which determine how the lock
detect block controls the integrated reclocker. Master mode is enabled when the
application layer sets the MASTER/SLAVE pin HIGH, and slave mode is enabled
when MASTER/SLAVE is set LOW.
The lock detect block controls the center frequency of the integrated reclocker to
ensure lock to the received serial digital data stream is achieved, and indicates via
the LOCKED output pin that the device has detected the appropriate sync words.
In Data through mode the detection for appropriate sync words is turned off. The
locked pin is an indication of analog lock.
Lock detection is a continuous process, which begins at device power up or after
a system reset, and continues until the device is powered down or held in reset.
The lock detection algorithm first determines if a valid serial digital input signal has
been presented to the device by sampling the internal carrier_detect signal. As
described in
serial digital input signal has been detected.
If the carrier_detect signal is HIGH, the serial data into the device is considered
invalid, and the VCO frequency will be set to the center of the pull range. The
LOCKED pin will be LOW and all outputs of the device except for the PCLK output
will be muted. Instead, the PCLK output frequency will operate within +/-3% of the
rates shown in
NOTE: When the device is operating in DVB-ASI slave mode only, the parallel
outputs will not mute when the carrier_detect signal is HIGH. The LOCKED signal
will function normally.
If a valid input signal has been detected, and the device is in master mode, the lock
algorithm will enter a hunt phase where four attempts are made to detect the
presence of either SMPTE TRS sync words or DVB-ASI sync words. At each
attempt, the center frequency of the reclocker will be toggled between 270Mb/s and
1.485Gb/s.
Assuming that a valid SMPTE or DVB-ASI signal has been applied to the device,
asynchronous lock times will be as listed in
In slave mode, the application layer fixes the center frequency of the reclocker such
that the lock algorithm will attempt to lock within the single data rate determined by
the setting of the SD/HD pin. Asynchronous lock times are also listed in the
Table
NOTE: The PCLK output will continue to operate during the lock detection process.
The frequency may toggle between 148MHz and 27MHz when the 20bit/10bit pin
is set LOW, or between 74MHz and 13.5MHz when 20bit/10bit is set HIGH.
30572 - 7
2-2.
May 2007
Carrier Detect Input on page
Table 4-16
of
Parallel Output Clock (PCLK) on page
27, this signal will be LOW when a good
Table
2-2.
GS1559 Data Sheet
62.
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