OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 25

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
UM10415
User manual
3.4.28 Start logic signal enable register 0
3.4.29 Start logic reset register 0
3.4.30 Start logic status register 0
This STARTERP0 register enables or disables the start signal bits in the start logic. The bit
assignment is identical to
Table 31.
Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit
assignment is identical to
clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt
for waking up from Deep-sleep mode. Therefore, the start-up logic states must be cleared
before being used.
Table 32.
This register reflects the status of the enabled start signal bits. The bit assignment is
identical to
or not a wake-up signal has been received for a given pin.
Table 33.
Bit
10:0
31:11 -
Bit
10:0
31:11
Bit
10:0
31:11
Symbol
ERPIO0_10 to
ERPIO0_0
Symbol
SRPIO0_10 to
SRPIO0_0
-
Symbol
RSRPIO0_10
to
RSRPIO0_0
-
Start logic signal enable register 0 (STARTERP0, address 0x4004 8204) bit
description
Start logic reset register 0 (STARTRSRP0CLR, address 0x4004 8208) bit
description
Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description
Table
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30. Each bit (if enabled) reflects the state of the start logic, i.e. whether
Rev. 1 — 10 September 2010
Value
0
1
Value
0
1
-
Value
0
1
-
Table
Table
Description
Enable start signal for start logic input PIO0_10 to
PIO0_0
Disabled
Enabled
Reserved
Description
Start signal status for start logic input PIO0_10 to
PIO0_0
No start signal received
Start signal pending
Reserved
Reserved
Description
Start signal reset for start logic input PIO0_10 to
PIO0_0
-
Write: reset start signal
30. The start-up logic uses the input signals to generate a
30.
Chapter 3: EM773 System configuration
UM10415
© NXP B.V. 2010. All rights reserved.
Reset
value
0x0
0x0
Reset
value
n/a
n/a
Reset
value
n/a
n/a
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