OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 26

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
UM10415
User manual
3.4.31 Deep-sleep mode configuration register
This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit
when the device enters Deep-sleep mode.
This register must be initialized at least once before entering Deep-sleep mode with
one of the four values shown in
Table 34.
Remark: Failure to initialize and program this register correctly may result in undefined
behavior of the microcontroller. The values listed in
for PDSLEEPCFG register.
To select the appropriate power configuration for Deep-sleep mode, consider the
following:
Configuration
BOD on
BOD off
•
•
BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event
occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an
additional current drain in Deep-sleep mode.
WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to
provide a clock for the watchdog timer or a general purpose timer if they are needed
for timing a wake-up event (see
oscillator analog output frequency must be set to its lowest value (bits FREQSEL in
the WDTOSCCTRL = 0001, see
clock must be disabled in the SYSAHBCLKCTRL register (see
entering Deep-sleep mode.
The watchdog oscillator, if running, contributes an additional current drain in
Deep-sleep mode.
Allowed values for PDSLEEPCFG register
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
WD oscillator on
PDSLEEPCFG = 0x0000 18B7 PDSLEEPCFG = 0x0000 18F7
PDSLEEPCFG = 0x0000 18BF PDSLEEPCFG = 0x0000 18FF
Table
Section 3.8.3
Table
34:
9) and all peripheral clocks other than the timer
Chapter 3: EM773 System configuration
for details). In this case, the watchdog
Table 34
WD oscillator off
are the only values allowed
Table
UM10415
© NXP B.V. 2010. All rights reserved.
17) before
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