OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 30
![BOARD EVAL EM773 METER US PLUG](/photos/38/74/387430/om13005_sml.jpg)
OM13005,598
Manufacturer Part Number
OM13005,598
Description
BOARD EVAL EM773 METER US PLUG
Manufacturer
NXP Semiconductors
Type
Other Power Managementr
Specifications of OM13005,598
Design Resources
Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
Main Purpose
Power Management, Energy/Power Meter
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
EM773FHN33,551
Interface Type
USB
Maximum Operating Temperature
+ 150 C
Operating Supply Voltage
1.8 V to 3.6 V
Product
Power Management Development Tools
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Primary Attributes
-
Secondary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
EM773, OL2381
Other names
568-6680
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NXP Semiconductors
3.5 Reset
3.6 Brown-out detection
3.7 Power management
UM10415
User manual
3.7.1 Active mode
Reset has four sources on the EM773: the RESET pin, Watchdog Reset, Power-On Reset
(POR), and Brown Out Detect (BOD). In addition, there is a software reset.
The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once
the operating voltage attains a usable level, starts the IRC causing reset to remain
asserted until the external Reset is de-asserted, the oscillator is running, and the flash
controller has completed its initialization.
On the assertion of a reset source external to the Cortex-M0 CPU (POR, BOD reset,
External reset, and Watchdog reset), the following processes are initiated:
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
The EM773 includes four levels for monitoring the voltage on the V
falls below one of the four selected levels, the BOD asserts an interrupt signal to the
NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC
in order to cause a CPU interrupt; if not, software can monitor the signal by reading the
NVIC status register (see
cause a forced reset of the chip (see
The EM773 supports a variety of power control features. In Active mode, when the chip is
running, power and clocks to selected peripherals can be optimized for power
consumption. In addition, there are three special modes of processor power reduction:
Sleep mode, Deep-sleep mode, and Deep power-down mode.
Remark: The Debug mode is not supported in Sleep, Deep-sleep, or Deep power-down
modes.
In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock,
and peripherals are clocked by the system clock or a dedicated peripheral clock.
The chip is in Active mode after reset and the default power configuration is determined
by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power
configuration can be changed during run time.
1. The IRC starts up. After the IRC-start-up time (maximum of 6 μs on power-up), the
2. The boot code in the ROM starts. The boot code performs the boot tasks and may
3. The flash is powered up. This takes approximately 100 μs. Then the flash initialization
IRC provides a stable clock output.
jump to the flash.
sequence is started, which takes about 250 cycles.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Table
46). An additional four threshold levels can be selected to
Table
28).
Chapter 3: EM773 System configuration
DD
UM10415
pin. If this voltage
© NXP B.V. 2010. All rights reserved.
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