OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 286

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
UM10415
User manual
20.5.3.5 System Control Register
Table 249. AIRCR bit assignments
The SCR controls features of entry to and exit from low power state. See the register
summary in
Table 250. SCR bit assignments
Bits
[31:16]
[15]
[14:3]
[2]
[1]
[0]
Bits
[31:5]
[4]
[3]
[2]
[1]
[0]
Name
-
SEVONPEND
-
SLEEPDEEP
SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread
-
Name
Read: Reserved
Write: VECTKEY
ENDIANESS
-
SYSRESETREQ
VECTCLRACTIVE
-
Table 20–246
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
for its attributes. The bit assignments are:
Function
Reserved.
Send Event on Pending bit:
0 = only enabled interrupts or events can wake-up the processor,
disabled interrupts are excluded
1 = enabled events and all interrupts, including disabled interrupts,
can wake-up the processor.
When an event or interrupt enters pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for
an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
Reserved.
Controls whether the processor uses sleep or deep sleep as its low
power mode:
0 = sleep
1 = deep sleep.
mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR to Thread
mode.
Setting this bit to 1 enables an interrupt driven application to avoid
returning to an empty main application.
Reserved.
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
Type
RW
RO
-
WO
WO
-
Function
Register key:
Reads as Unknown
On writes, write 0x05FA to VECTKEY, otherwise the
write is ignored.
Data endianness implemented:
0 = Little-endian
1 = Big-endian.
Reserved
System reset request:
0 = no effect
1 = requests a system level reset.
This bit reads as 0.
Reserved for debug use. This bit reads as 0. When
writing to the register you must write 0 to this bit,
otherwise behavior is Unpredictable.
Reserved.
UM10415
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