EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 119

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 6–10. Cyclone III PLL Ports
Notes to
(1)
(2)
Altera Corporation-Preliminary
March 2007
You can feed inclk0 or inclk1 clock input from any one of the four clock pins located on the same side of the
device as the PLL. This input port can also be fed by an output from another PLL, a pin-driven dedicated global
clock, or through a clock control block if the clock control block is fed by an output from another PLL or a pin-driven
dedicated global clock. An internally generated global signal cannot drive the PLL.
You can drive to global clock network (C[4..0]) or dedicated external clock output pins (only C0).
Figure
6–10:
f
inclk0 (1)
inclk1 (1)
clkswitch
areset
pfdena
scanclk
scandata
scanclkena
configupdate
phasecounterselect[2..0]
phaseupdown
phasestep
Refer to the Cyclone III Device I/O Features chapter of the Cyclone III Device
Handbook, Volume 1, to determine which I/O standards are supported by
the PLL clock input and output pins.
Cyclone III PLLs can also drive out to any regular I/O pin through the
global clock network. You can also use the external clock output pins for
general purpose I/O pins if you do not need external PLL clocking.
Cyclone III PLL Software Overview
The altpll megafunction in Quartus II software enables the Cyclone III
PLLs.
altpll megafunction of the Quartus II software.
Notes
Figure 6–10
(1),
(2)
shows the Cyclone III PLL ports as named in the
scandataout
clkbad[1..0]
phasedone
activeclock
(2) C[4..0]
scandone
locked
Cyclone III Device Handbook, Volume 1
Signal Driven by Internal Logic
internal logic or I/O pins
Internal Clock Signal
Signal driven to
Physical Pin
or I/O pins
Cyclone III PLL
6–19