EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 329

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
DATA[15..8]
PADD[23..0]
nRESET
nAVD
nOE
Table 10–21. Dedicated Configuration Pins on the Cyclone III Device (Part 6 of 7)
Pin Name
I/O
N/A in AP
mode. I/O in
non-AP
mode
N/A in AP
mode. I/O in
non-AP
mode
N/A in AP
mode. I/O in
non-AP
mode
N/A in AP
mode. I/O in
non-AP
mode
User Mode
AP
AP
AP
AP
AP
Configuration
Scheme
Bidirectional
open-drain
Output
Output
Output
Output
Pin Type
Data inputs. Word-wide configuration data is
presented to the target Cyclone III device on
DATA[15..0]
In PS, FPP or AS configuration schemes, they
function as user I/O pins during configuration,
which means they are tri-stated.
After AP configuration,
dedicated bidirectional pins with optional user
control.
24-bit address bus from the Cyclone III device
to the parallel flash in AP mode. Connects to
the
A[23..0]
flash.
Active-low reset output. Driving the
pin low resets the parallel flash. Connects to
the
pin on the Spansion S29WS-N flash.
Active-low address valid output. Driving the
nAVD
indicates to the parallel flash that valid
address is present on the
address bus. Connects to the
Intel P30 or the
S29WS-N flash.
Active-low output enable to the parallel flash.
Driving the
enables the parallel flash outputs
(
OE#
Spansion S29WS-N flash.
DATA[15..0]
A[24:1]
RST#
Cyclone III Device Handbook, Volume 1
pin on both the Intel P30 and the
pin low during read or write operation
pin on the Intel P30 or the
nOE
bus on the Spansion S29WS-N
bus on the Intel P30 or the
.
AVD#
pin low during read operation
Description
and
Device Configuration Pins
RDY
pin on the Spansion
DATA[15:8]
PADD[23..0]
). Connects to the
ADV#
nRESET
pin on the
RESET#
are
10–93