EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 231

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
f
The two DDR output registers are located in the I/O element (IOE) block.
Two serial data streams routed through datain_l and datain_h, are
fed into two registers, output register A
B
register A
output from output register B
clock. The registered outputs are multiplexed by the common clock to
drive the DDR output pin at twice the data rate.
The DDR output enable path has a similar structure to the DDR output
path in the IOE block. The second output enable register provides the
write preamble for the DQS strobe in DDR external memory interfaces.
This active-low output enable register extends the high-impedance state
of the pin by half a clock cycle to provide the external memory’s DQS write
preamble time specification.
enable register extends the DQS high-impedance state by half a clock cycle
during a write operation.
For more information on the Cyclone III IOE registers, refer to the
Cyclone III Device I/O Features chapter in volume 1 of the Cyclone III
Device Handbook.
o
, respectively, on the same clock edge. The output from output
o
is captured on the falling edge of the clock, while the
Figure 9–8
o
Cyclone III Device Handbook, Volume 1
Cyclone III Memory Interfaces Features
is captured on the rising edge of the
illustrates how the second output
o
and output register
9–17