EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 288

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Configuring Cyclone III Devices
10–52
Cyclone III Device Handbook, Volume 1
integrity and prevent clock skew problems. Ensure that the DCLK and
DATA lines are buffered. Because all device CONF_DONE pins are tied
together, all devices initialize and enter user mode at the same time.
If any device detects an error, configuration stops for the entire chain and
the entire chain must be reconfigured because all nSTATUS and
CONF_DONE pins are tied together. For example, if the first device flags an
error on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices release their nSTATUS pins after a reset time-out period
(maximum of 80 µs). After all nSTATUS pins are released and pulled high,
the MAX II device can try to reconfigure the chain without needing to
pulse nCONFIG low. If this option is turned off, the MAX II device must
generate a low-to-high transition (with a low pulse of at least 500 ns) on
nCONFIG to restart the configuration process.
In your system, you can have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[0], and
CONF_DONE) are connected to every device in the chain. Configuration
signals can require buffering to ensure signal integrity and prevent clock
skew problems. Ensure that the DCLK and DATA lines are buffered.
Devices must be the same density and package. All devices will start and
complete configuration at the same time.
device PS configuration when both Cyclone III devices are receiving the
same configuration data.
Figure 10–16
Altera Corporation-Preliminary
shows multi-
March 2007