EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 358

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Remote System Upgrade With Cyclone III Devices
12–18
Cyclone III Device Handbook, Volume 1
RU_nRSTIMER
RU_nCONFIG
RU_CLK
Table 12–11. Interface Signals Between Remote System Upgrade Circuitry and Cyclone III Device Logic
Array (Part 1 of 2)
Signal Name
Input to remote system
upgrade block (driven by
device logic array)
Input to remote system
upgrade block (driven by
device logic array)
Input to remote system
upgrade block (driven by
device logic array)
Signal Direction
control, status, and update registers using the remote system upgrade
shift register.
their functionality.
Except for RU_nRSTIMER and RU_CAPTnUPDT, the logic array signals are
enabled for remote update mode and for both factory and application
configurations. RU_nRSTIMER is only valid for application
configurations in remote update mode, since factory configurations have
the user watchdog timer disabled. When RU_CAPTnUPDT is low, the
device can write to the update register only for factory configurations in
remote update mode, since this is the only case where the update register
is written to by the user logic. When the RU_nCONFIG signal goes high,
the contents of the update register are written into the control register for
controlling the next configuration cycle.
Table 12–11
Request from the application configuration to reset the user
watchdog timer with its initial count. A falling edge of this signal
triggers a reset of the user watchdog timer.
When driven low, this signal triggers the device to reconfigure.
If asserted by the factory configuration in remote update
mode, the application configuration specified in the remote
update control register is loaded. If requested by the
application configuration in remote update mode, the factory
configuration is loaded.
Clocks the remote system upgrade shift register and update
register so that the contents of the status, control, and update
registers can be read, and so that the contents of the update
register can be loaded. The shift register latches data on the
rising edge of this clock signal.
lists each of these seven signals and describes
Description
Altera Corporation-Preliminary
March 2007