EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 135

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 6–20. Delay Insertion Using VCO Phase Output and Counter Delay Time
PLL Cascading
Altera Corporation-Preliminary
March 2007
You can use the coarse and fine phase shifts to implement clock delays in
Cyclone III devices.
Cyclone III devices support dynamic phase shifting of VCO phase taps
only. The phase shift is configurable for any number of times, and each
phase shift takes about one SCANCLK cycle, allowing you to implement
large phase shifts quickly.
Two PLLs may be cascaded to each other through the clock network. If the
design cascades PLLs, the source (upstream) PLL should have a
high-bandwidth setting, while the destination (downstream) PLL should
have a low-bandwidth setting.
cascading PLLs.
Figure 6–21
Cyclone III Device Handbook, Volume 1
shows usage of GCLK while
PLL Cascading
6–35