EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 434
EP3C16F256I7
Manufacturer Part Number
EP3C16F256I7
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C16F256I7.pdf
(582 pages)
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Switching Characteristics
1–24
Cyclone III Handbook
Notes to
(1)
(2)
(3)
Notes to
(1)
(2)
(3)
t
t
t
f
Device operation in Mbps
t
TCCS
Output jitter (peak to peak)
t
t
t
RISE
FALL
LOCK
HSCLK
DUTY
RISE
FALL
LOCK
Table 1–29. Three-Resistor PPDS Transmitter Timing Specification (2),
Table 1–30. Dedicated Mini-LVDS Transmitter Timing Specification
Pending silicon characterization.
Values for device speed grade -7 and -8 will be available after characterization.
Three-resistor PPDS is only supported at output pin of Column I/O (Bank 3, 4, 7 and 8).
Pending silicon characterization.
Values for device speed grade -7 and -8 will be available after characterization.
Dedicated mini-LVDS is only supported at output pin of Row I/O (Bank 1, 2, 5 and 6).
(input clock frequency)
Table
Table
Symbol
Symbol
1–29:
1–30:
20–80%
80–20%
Modes
20–80%
80–20%
Modes
x10
x10
x8
x7
x4
x2
x1
x8
x7
x4
x2
x1
(1)
Min
100
Min
10
10
10
10
10
10
80
70
40
20
10
(2)
,
-6 Speed Grade
-6 Speed Grade
(3)
(3)
(1)
(1)
Altera Corporation- Preliminary
(Part 2 of 2)
Typ
Typ
(1)
(1)
(1)
1.30
(1)
(1)
Max
Max
200
200
200
200
200
400
400
400
400
400
400
400
(1)
March 2007
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ps
ps
ms
ns
ps
ps
ps
%
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