EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 442

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

I/O Timing
1–32
Cyclone III Handbook
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum
voltage, and maximum temperature for input register setup time (t
and hold time (
to calculate t
Figure 1–1
Figure 1–1. Input Register Setup & Hold Timing Diagram
For output timing, different I/O standards require different baseline
loading techniques for reporting timing delays. Altera characterizes
timing delays with the required termination for each I/O standard and
with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the
timing is specified up to the output pin of the FPGA device. The
Quartus II software calculates the I/O timing for each I/O standard with
a default baseline loading as specified by the I/O standards.
Note to
(1)
Table 1–40. Cyclone III Device Timing Model Status
t
t
EP3C120
Device EP3C5 information is not available at current version Quartus II.
H
SU
EP3C55
EP3C80
Device
= – data delay from input pin to input register
Table
= + data delay from input pin to input register
+ micro setup time of the input register
– clock delay from input pin to input register
+ micro hold time of the input register
+ clock delay from input pin to input register
shows the setup and hold timing diagram for input registers.
SU
1–40:
and
t
H
). The Quartus II software uses the following equations
t
H
Preliminary
timing for Cyclone III devices input signals:
Input Clock Delay
Input Data Delay
v
v
v
Correlated
Altera Corporation- Preliminary
micro t
micro t
SU
H
Final
March 2007
SU
)