EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 389

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 14–10. IEEE Std. 1149.1 BST EXTEST Mode
Altera Corporation-Preliminary
March 2007
Capture Phase
In the capture phase, the signals at the
pin, OEJ and OUTJ, are loaded into the
capture registers. The CLOCK signals
are supplied by the TAP controller's
CLOCKDR output. Previously retained
data in the update registers drive the
PIN_OUT, INJ and allows the I/O pin
to tri-state or drive a signal out.
A "1" in the OEJ update register tri-states
the output buffer.
Shift & Update Phases
In the shift phase, the previously captured
signals at the pin, OEJ and OUTJ, are
shifted out of the boundary-scan register
via the TDO pin using CLOCK. As data is
shifted out, the patterns for the next test
can be shifted in via the TDI pin.
In the update phase, data is transferred
from the capture registers to the update
registers using the UPDATE clock. The
update registers then drive the PIN_IN,
INU, and allow the I/O pin to tri-state or
drive a signal out.
Figure 14–10
mode.
OUTJ
OUTJ
OEJ
OEJ
shows the capture, shift, and update phases of the EXTEST
SDI
SDI
0
1
0
1
0
1
0
1
0
1
0
1
SHIFT
SHIFT
CLOCK
CLOCK
Registers
D
D
D
Registers
Capture
D
D
D
Capture
Q
Q
Q
Q
Q
Q
IEEE Std. 1149.1 BST Operation Control
SDO
Cyclone III Device Handbook, Volume 1
SDO
UPDATE
UPDATE
D
D
D
Registers
D
D
D
Registers
Update
Update
Q
Q
Q
Q
Q
Q
0
1
0
1
0
1
0
1
0
1
0
1
MODE
MODE
INJ
INJ
14–15