EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 385

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 14–6. IEEE Std. 1149.1 Timing Waveforms
Notes to Figure 6:
(1)
Altera Corporation-Preliminary
March 2007
For JTAG timing parameters, please refer to the DC andSwitching Characteristics chapter in the Cyclone III Device
Handbook.
Captured
Driven
Signal
Signal
to be
to be
TMS
TDO
TCK
TDI
t
JCH
When the TAP controller is in the TEST_LOGIC/RESET state, the BST
circuitry is disabled, the device is in normal operation, and the instruction
register is initialized with IDCODE as the initial instruction. At device
power-up, the TAP controller starts in this TEST_LOGIC/RESET state. In
addition, forcing the TAP controller to the TEST_LOGIC/RESET state is
done by holding TMS high for five TCK clock cycles. Once in the
TEST_LOGIC/RESET state, the TAP controller remains in this state as
long as TMS is held high (while TCK is clocked).
timing requirements for the IEEE Std. 1149.1 signals.
To start IEEE Std. 1149.1 operation, select an instruction mode by
advancing the TAP controller to the shift instruction register (SHIFT_IR)
state and shift in the appropriate instruction code on the TDI pin. The
waveform diagram in
code into the instruction register.
TMS, TDI, TDO, and the states of the TAP controller. From the RESET state,
TMS is clocked with the pattern 01100 to advance the TAP controller to
SHIFT_IR.
t
t
JSZX
JPZX
t
JCP
t
JSSU
t
JCL
t
JSH
t
t
(1)
JPCO
JSCO
Figure 14–7
t
JPSU
Figure 14–7
IEEE Std. 1149.1 BST Operation Control
represents the entry of the instruction
Cyclone III Device Handbook, Volume 1
t
t
JPH
JSXZ
t
JPXZ
shows the values of TCK,
Figure 14–6
shows the
14–11