EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 198

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

High-Speed Differential Interfaces in Cyclone III Devices
Figure 8–4. LVDS Interface with External Resistor Network on the Top and Bottom I/O Banks
Note to
(1)
Figure 8–5. Transmitter Output Waveforms for the LVDS Differential I/O Standard
Note to
(1)
8–8
Cyclone III Device Handbook, Volume 1
The
The p – n waveform is a function of the positive channel (
Figure
Figure
R
S
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
and
Cyclone III Device
8–4:
8–5:
LVDS Transmitter
Non-Dedicated
R
P
values are pending device characterization.
V
OS
Figure 8–5
LVDS Receiver
Cyclone III LVDS receivers support a data rate up to 875 Mbps. All the
Cyclone III device I/O banks support dedicated receivers. The maximum
internal clock frequency for the receiver is 437.5 MHz.
V OD
Resistor Network
R S
R S
shows the signaling level for LVDS transmitter outputs.
V
OD
R P
p
) and the negative channel (
50 Ω
50 Ω
V OD
0 V
p − n (1)
100 Ω
Positive Channel (p) = V
Negative Channel (n) = V
Ground
Altera Corporation-Preliminary
LVDS Receiver
n
).
OH
OL
March 2007