EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 308

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Configuring Cyclone III Devices
10–72
Cyclone III Device Handbook, Volume 1
TMS
TCK
Pin Name
Table 10–14. Dedicated JTAG Pins
Test mode select Input pin that provides the control signal to determine the transitions of the TAP
Test clock input
Pin Type
You can download data to the device on the PCB through the USB Blaster,
MasterBlaster, ByteBlaster II, or ByteBlasterMV download cable during
JTAG configuration. Configuring devices through a cable is similar to
programming devices in-system.
of a single Cyclone III device.
The clock input to the BST circuitry. Some operations occur at the rising edge,
controller state machine. Transitions within the state machine occur on the rising
edge of
is evaluated on the rising edge of
the board, the JTAG circuitry can be disabled by connecting this pin to VCC.
while others occur at the falling edge. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting this pin to GND.
TCK
. Therefore,
TMS
must be set up before the rising edge of
TCK
Description
Figure 10–24
. If the JTAG interface is not required on
Altera Corporation-Preliminary
shows JTAG configuration
March 2007
TCK
.
TMS