EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 36

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Logic Elements and Logic Array Blocks in Cyclone III Devices
Figure 2–4. LE in Normal Mode
2–6
Cyclone III Device Handbook, Volume 1
data1
data2
data3
cin (from cout
of previous LE)
data4
Packed Register Input
Normal Mode
The normal mode is suitable for general logic applications and
combinational functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see
Quartus II Compiler automatically selects the carry-in (cin) or the data3
signal as one of the inputs to the LUT. LEs in normal mode support
packed registers and register feedback.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters,
accumulators, and comparators. An LE in arithmetic mode implements a
2-bit full adder and basic carry chain
can drive out registered and unregistered versions of the LUT output.
Register feedback and register packing are supported when LEs are used
in arithmetic mode.
Four-Input
LUT
Register Chain
Connection
Register Bypass
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
(LAB Wide)
Register Feedback
sclear
(Figure
ENA
D
CLRN
Q
Altera Corporation-Preliminary
2–5). LEs in arithmetic mode
Figure
Row, Column, and
Direct Link Routing
Row, Column, and
Direct Link Routing
Local Routing
Register
Chain Output
2–4). The
March 2007