XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 200

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
Each of the eight framers within the XRT84L38 includes a Transmit Payload Data Input Interface block. The
function of this block is to provide an interface to the local Terminal Equipment (for example, a Central Office or
switching equipment) that has data to send to a Far End terminal over a DS1 or E1 transport medium.
The Payload Data Input Interface module (also known as the Back-plane Interface module) supports payload
data to be taken from or presented to the system. In DS1 mode, supported data rates are 1.544Mbit/s, MVIP
2.048Mbit/s, 4.096Mbit/s, 8.192Mbit/s, multiplexed 12.352Mbit/s, multiplexed 16.384Mbit/s, HMVIP 16.384Mbit/s
or H.100 16.384Mbit/s. In E1 mode, supported data rates are XRT84V24 compatible 2.048Mbit/s, MVIP
2.048Mbit/s, 4.096Mbit/s, 8.192Mbit/s, multiplexed 16.384Mbit/s, HMVIP 16.384Mbit/s or H.100 16.384Mbit/s.
The Transmit Payload Data Input Interface block supplies or accepts the following signals to the local Terminal
Equipment circuitry:
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The Transmit Serial Data is an input pin carrying payload, signaling and sometimes Data Link data supplied by
the local Terminal Equipment to the XRT84L38.
The Transmit Serial Clock is an input or output signal used by the Transmit Payload Data Input Interface block to
latch in incoming serial data from the local Terminal Equipment. The Transmit Clock Inversion bit of the Transmit
Interface Control Register (TICR) determines at which edge of the Transmit Serial Clock would data transition on
the Transmit Serial Data pin occur.
The table below shows configurations of the Transmit Clock Inversion bit of the Transmit Interface Control
Register (TICR).
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0xn0H, 0x20H)
Throughout the discussion of this datasheet, we assume that serial data transition happens on the rising edge of
the Transmit Serial Clock unless stated otherwise.
The Transmit Single-frame Synchronization signal is either input or output. When configured as input, it indicates
the beginning of a DS1 frame. When configured as output, it indicates the end of a DS1 frame.
The Transmit Multi-frame Synchronization signal is either input or output. When configured as input, it indicates
the beginning of a DS1 multi-frame. When configured as output, it indicates the end of a DS1 multi-frame.
The Transmit Input Clock signal is multiplexed into the Transmit Multi-frame Synchronization pin (TxMSync_n) of
XRT84L38. When the framer is running at High-speed Back-plane Interface mode, the Transmit Input Clock
functions as the timing source for the High-speed Back-plane Interface.
4.0 THE DS1 TRANSMIT SECTION
4.1
4.1.1
N
Transmit Serial Data Input (TxSer_n)
Transmit Serial Clock (TxSerClk_n)
Transmit Single-frame Synchronization Signal (TxSync_n)
Transmit Multi-frame Synchronization Signal (TxMSync_n)
Transmit Time-slot Indicator Clock (TxTSClk_n)
Transmit Time-slot Indication Bits (TxTSb[4:0]_n)
UMBER
B
3
IT
The DS1 Transmit Payload Data Input Interface Block
Description of the Transmit Payload Data Input Interface Block
Transmit Clock
B
Inversion
IT
N
AME
B
IT
R/W
T
YPE
0 - Serial data transition happens on rising edge of the Transmit Serial Clock.
1 - Serial data transition happens on falling edge of the Transmit Serial Clock.
180
B
IT
D
ESCRIPTION
REV. 1.0.1