XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 259

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XRT84L38IB

Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet

Specifications of XRT84L38IB

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
REV. 1.0.1
See
Interface block of the framer in Bit-multiplexed 16.384Mbit/s mode.
The Input signal timing is shown in
s mode.
When the Receive Multiplex Enable bit is set to one and the Receive Interface Mode Select [1:0] bits are set to
10, the Receive Back-plane interface of framer is running at a clock rate of 16.384MHz.
The interface consists of the following pins:
F
F
16.384M
5.1.3.6
IGURE
IGURE
Data input (RxSer_n)
Receive Serial Clock Input signal (RxSerClk_n)
Receive Single-frame Synchronization Input signal (RxSync_n)
Receive Input Clock (RxInClk_n)
Receive Time-slot Indication clock (RxTSClk_n)
Receive Time Slot indicator bits (RxTSb[4:0]_n)
RxSerClk (16.384MHz)
RxSerClk (INV)
RxSer
RxSync(input)
Figure 57
57. I
58. T
BIT
/
S
NTERFACING
IMING
T1 Receive Input Interface - HMVIP 16.384Mbit/s
below for how to interface the local Terminal Equipment with the Receive Payload Data Output
D
F
IAGRAM OF
0
F
0
Equipment
F
Terminal
1
XRT84L38
F
1
F
2
F
2
F
I
3
NPUT SIGNALS TO THE
F
3
Figure 58
TO LOCAL
56 cycles
RxSerClk_4 (16.384MHz)
RxSer_4
RxMSync_4
RxSync_4
RxSerClk_0 (16.384MHz)
RxSer_0
RxMSync_0
RxSync_0
below when the framer is running at Bit-Multiplexed 16.384Mbit/
T
1
ERMINAL
0
X 1
1
239
X
F
1
2
RAMER WHEN RUNNING AT
X
E
1
QUIPMENT USING
3
X
2
0
X 2
1
X
Data Input
Data Input
Interface
Interface
Receive
Receive
Payload
Chn 0-3
Payload
Chn 4-7
3
0
X
16.384M
XRT84L38
4
0
OCTAL T1/E1/J1 FRAMER
B
X
IT
BIT
-
MULTIPLEXED
/
S
5
0
A
D
0
ATA
5
1
A
1
XRT84L38
5
B
2
A
US
2
5
3
A
3

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