XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 39

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
RECEIVE SERIAL DATA OUTPUT
(Framer Channel Number indicated by _n)
S
RxSerClk_0
RxSerClk_1
RxSerClk_2
RxSerClk_3
RxSerClk_4
RxSerClk_5
RxSerClk_6
RxSerClk_7
IGNAL
RxSer_0
RxSer_1
RxSer_2
RxSer_3
RxSer_4
RxSer_5
RxSer_6
RxSer_7
N
AME
AF25
AD15
AE23
AE16
P
W26
AD7
AD8
A17
E23
U24
C18
B24
D4
B2
B9
A9
IN
#
I or O
T
YPE
O
Receive Serial Clock Signal—Receive Framer_n: (Continued)
Receive Back-plane Interface-Multiplexed at 16.384 MHz Clock Mode
If RxMUXEN = 1 and RxIMODE[1:0] = 01 in Receive interface control register,
Receive back-plane interface of Framer_n is presenting bit-multiplexed data at a
rate of 16.384 Mbit/s. RxSerClk_0 and RxSerClk_4 signals will be Input clock
signals running at 16.384 MHz. RxSerClk_1, 2, 3 and RxSerClk_5, 6, 7 signals
are not required. Received DS1 Payload data of Channel 0, 1, 2 and 3 are mul-
tiplexed and latched out from Receive back-plane interface using clock edge of
RxSerClk_0 via RxSer_0 output pin. Receive DS1 Payload data of Channel 4,
5, 6 and 7 are multiplexed and latched out from Receive back-plane interface
using clock edge of RxSerClk_4 via RxSer_4 output pin.
Receive Back-plane Interface-HMVIP, 16.384 MHz Clock Mode
If RxMUXEN = 1 and RxIMODE[1:0] = 10 in Receive interface control register,
Receive back-plane interface of Framer_n is presenting multiplexed data at a
rate of 16.384 Mbit/s. RxSerClk_0 and RxSerClk_4 signals will be Input clock
signals running at 16.384 MHz. RxSerClk_1, 2, 3 and RxSerClk_5, 6, 7 signals
are not required. Received DS1 Payload data of Channel 0, 1, 2 and 3 are mul-
tiplexed and latched out from Receive back-plane interface using clock edge of
RxSerClk_0 via RxSer_0 output pin. Receive DS1 Payload data of Channel 4,
5, 6 and 7 are multiplexed and latched out from Receive back-plane interface
using clock edge of RxSerClk_4 via RxSer_4 output pin.
Receive Back-plane Interface-H.100, 16.384 MHz Clock Mode
If RxMUXEN = 1 and RxIMODE[1:0] = 11 in Receive interface control register,
Receive back-plane interface of Framer_n is presenting multiplexed data at a
rate of 16.384 Mbit/s. RxSerClk_0 and RxSerClk_4 signals will be Input clock
signals running at 16.384 MHz. RxSerClk_1, 2, 3 and RxSerClk_5, 6, 7 signals
are not required. Received DS1 Payload data of Channel 0, 1, 2 and 3 are mul-
tiplexed and latched out from Receive back-plane interface using clock edge of
RxSerClk_0 via RxSer_0 output pin. Receive DS1 Payload data of Channel 4,
5, 6 and 7 are multiplexed and latched out from Receive back-plane interface
using clock edge of RxSerClk_4 via RxSer_4 output pin.
Receive Serial Data Output—Receive Framer_n:
This output pin along with RxSerClk_n functions as the Receive Serial Output
port for Framer_n.
T1 mode:
Any incoming T1 line data that is received from the RxPOS_n and RxNEG_n
input pins, will be decoded and output via this pin.Framer_n can use either the
rising edge or the falling edge of RxSerClk_n input pin to latch the received T1
payload data out according to configurations of Framer_n.
E1 mode:
Much of the data that is received from the line via the RxPOS_n and RxNEG_n
input pins, will be decoded and output via this pin, in a binary format.All data that
is transported via Time Slots 1 through 15 and Time Slots 17 through 31, within
each incoming E1 frame, will be output via this pin. If Framer_n is configured
accordingly, the data for Time Slots 0 and 16 will also be output via this pin.
Framer_n can use either the rising edge or the falling edge of RxSerClk_n input
pin to latch the received DS1/E1 payload data out according to configurations of
Framer_n.
19
D
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38