XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 256

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XRT84L38IB

Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet

Specifications of XRT84L38IB

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
XRT84L38
OCTAL T1/E1/J1 FRAMER
See
Interface block of the framer in 12.352Mbit/s mode.
The Input signal timing is shown in
When the Receive Multiplex Enable bit is set to one and the Receive Interface Mode Select [1:0] bits are set to
01, the Receive Back-plane interface of framer is running at a clock rate of 16.384MHz.
The interface consists of the following pins:
The Receive Back-plane Interface is pumping out data through RxSer_0 or RxSer_4 pins at 16.384Mbit/s. It
multiplexes payload and signaling data of every four channels into one data stream. Payload and signaling
F
F
5.1.3.5
IGURE
IGURE
Data input (RxSer_n)
Receive Serial Clock Input signal (RxSerClk_n)
Receive Single-frame Synchronization Input signal (RxSync_n)
Receive Input Clock (RxInClk_n)
Receive Time-slot Indication clock (RxTSClk_n)
Receive Time Slot indicator bits (RxTSb[4:0]_n)
RxSerClk (12.352MHz)
RxSerClk (INV)
RxSer
RxSync(input)
Figure 55
55. I
56. T
NTERFACING
IMING
T1 Receive Input Interface - Bit-Multiplexed 16.384Mbit/s
below for how to interface the local Terminal Equipment with the Receive Payload Data Output
D
F
IAGRAM OF
0
F
0
Equipment
F
Terminal
1
XRT84L38
F
1
F
2
F
2
F
I
3
NPUT SIGNALS TO THE
F
3
1
Figure 56
0
TO LOCAL
X 1
1
X
1
RxSerClk_4 (12.352MHz)
RxSer_4
RxMSync_4
RxSync_4
RxSerClk_0 (12.352MHz)
RxSer_0
RxMSync_0
RxSync_0
2
X
1
below when the framer is running at 12.352Mbit/s mode.
3
T
X
ERMINAL
2
0
X 2
236
1
F
X
RAMER WHEN RUNNING AT
E
QUIPMENT USING
3
0
X
4
0
X
Data Input
Data Input
Interface
Interface
Receive
Receive
Payload
Chn 0-3
Payload
Chn 4-7
5
12.352M
XRT84L38
0
A
0
5
1
A
1
12.352M
5
2
A
BIT
2
5
3
/
A
S
3
6
D
BIT
0
ATA
B
0
6
/
1
S
B
B
1
6
US
2
B
2
6
REV. 1.0.1
3
B
3

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