XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 403

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
If there is no valid AIS16 flag, the Alarm indication logic will decrement the flag counter. The AIS16 alarm is
removed when the counter reaches 0.
The Alarm Indication Signal Detection Select [1:0] bits of the Alarm Generation Register (AGR) enable the
three types of AIS detection that are supported by the XRT84L38 framer. The table below shows configurations
of the Alarm Indication Signal Detection Select [1:0] bits of the Alarm Generation Register (AGR).
ALARM GENERATION REGISTER (AGR) (INDIRECT ADDRESS = 0XN0H, 0X08H)
If detection of unframed or framed AIS alarm is enabled by the user and if AIS is present in the incoming E1
frame, the XRT84L38 framer can generate a Receive AIS State Change interrupt associated with the setting of
Receive AIS State Change bit of the Alarm and Error Status Register to one.
To enable the Receive AIS State Change interrupt, the Receive AIS State Change Interrupt Enable bit of the
Alarm and Error Interrupt Enable Register (AEIER) have to be set to one. In addition, the Alarm and Error
Interrupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Receive AIS State Change Interrupt Enable bit of the Alarm and
Error Interrupt Enable Register (AEIER).
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER)
0X03H)
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H)
When these interrupt enable bits are set and AIS is present in the incoming E1 frame, the XRT84L38 framer
will declare AIS by doing the following:
•
•
N
N
N
Set the read-only Receive AIS State bit of the Alarm and Error Status Register (AESR) to one indicating
there is AIS alarm detected in the incoming E1 frame.
Set the Receive AIS State Change bit of the Alarm and Error Status Register to one indicating there is a
change in state of AIS. This status indicator is valid until the Framer Interrupt Status Register is read.
UMBER
UMBER
UMBER
B
1-0
B
B
1
1
IT
IT
IT
Receive AIS State
Change Interrupt
Alarm and Error
Interrupt Enable
AIS Detection
B
B
B
Enable
IT
Select
IT
IT
N
N
N
AME
AME
AME
B
B
B
IT
IT
IT
R/W
R/W
R/W
T
T
T
YPE
YPE
YPE
00 - AIS alarm detection is disabled.
01 - Detection of unframed AIS alarm of all ones pattern is enabled.
10 - Detection of AIS16 alarm is enabled.
11 - Detection of framed AIS alarm of all ones pattern except for framing
bits is enabled.
0 - The Receive AIS State Change interrupt is disabled.
1 - The Receive AIS State Change interrupt is enabled.
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.
383
B
B
B
IT
IT
IT
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
(INDIRECT ADDRESS = 0XNAH,
OCTAL T1/E1/J1 FRAMER
XRT84L38