XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 226

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The interface consists of the following pins:
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The Transmit Back-plane Interface is accepting data through TxSer_0 or TxSer_4 pins at 16.384Mbit/s. The local
Terminal Equipment multiplexes payload and signaling data of every four channels into one data stream. Payload
and signaling data of Channel 0-3 are multiplexed onto the Transmit Serial Data pin of Channel 0. Payload and
signaling data of Channel 4-7 are multiplexed onto the Transmit Serial Data pin of Channel 4.
Free-running clocks of 16.384MHz is supplied to the Transmit Input Clock pin of Channel 0 and Channel 4 of the
framer. The local Terminal Equipment provides multiplexed payload data at rising edge of this Transmit Input
Clock. The Transmit High-speed Back-plane Interface of the framer then latches incoming serial data at falling
edge of the clock.
The local Terminal Equipment maps four 1.544Mbit/s DS1 data streams into this 16.384Mbit/s data stream as
described below:
FIRST OCTET OF 16.384MBIT/S DATA STREAM
F
NINTH OCTET OF 16.384MBIT/S DATA STREAM
1. The F-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data
2. After the first octet of data is sent, the local Terminal Equipment should insert seven octets (fifty-six bits) of
3. Payload data of four channels are repeated and grouped together in a byte-interleaved way. The first pay-
X
Data input (TxSer_n)
Transmit Serial Clock Input signal (TxSerClk_n)
Transmit Single-frame Synchronization Input signal (TxSync_n)
Transmit Input Clock (TxInClk_n)
Transmit Time-slot Indication clock (TxTSClk_n)
Transmit Time Slot indicator bits (TxTSb[4:0]_n)
: F-bit of Channel X
stream. The F-bit of Channel 0 is sent first, followed by F-bit of Channel 1 and 2. The F-bit of Channel 3 is
sent last. The table below shows bit-pattern of the first octet.
"don't care" data into the outgoing data stream.
load bit of Timeslot 0 of Channel 0 is sent first, followed by the second payload bit of Timeslot 0 of Channel
0 and so on. After all the bits of Timeslot 0 of Channel 0 is sent repeatedly, the Terminal Equipment will
start sending the payload bits of Timeslot 0 of Channel 1 and 2. The payload bits of Timeslot 0 of Channel
3 are sent the last. After the payload bits of Timeslot 0 of all four channels are sent, it comes the payload
bits of Timeslot 1 of Channel 0 and so on. The table below demonstrates how payload bits of four channels
are mapped into the 16.384Mbit/s data stream.
B
B
F
1
IT
IT
0
0
0
0
B
B
F
1
IT
IT
0
0
1
1
B
B
F
2
IT
IT
0
1
2
2
B
B
F
2
IT
IT
0
1
3
3
206
B
B
F
3
IT
IT
2
0
4
4
B
B
F
3
IT
IT
2
0
5
5
B
B
F
4
IT
IT
3
0
6
6
REV. 1.0.1
B
B
F
4
IT
IT
3
0
7
7