XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 268

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
By connecting these signals with the local Terminal Equipment, the Transmit Payload Data Input Interface
accepts payload data from the Terminal Equipment and routes it to the Transmit Framer module inside the
device.
If the framer is operating in normal 2.048Mbit/s Back-plane interface mode for E1, timing source of the transmit
section can be one of the three clocks:
•
•
•
The Transmit Timing Source Select [1:0] bits of the Clock Select Register (CSR) determine which clock is used
as the timing source. The following table shows configurations of the Transmit Timing Source Select [1:0] bits
of the Clock Select Register.
CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H)
6.1.2
N
Transmit Serial Input Clock
OSCCLK Driven Divided Clock
Recovered Receive Line Clock
UMBER
B
1-0
IT
Brief Discussion of the Transmit Payload Data Input Interface Block Operating at XRT84V24
Compatible 2.048Mbit/s mode
Transmit Timing
Source Select
B
IT
N
AME
B
IT
R/W
T
YPE
Transmit Timing Source Select:
These two READ/WRITE bit-fields permit the user to select the timing source of
Transmit section of the framer.
When the Transmit Back-plane interface is operating at a clock rate of 2.048MHz
for E1, these two READ/WRITE bit-fields also determine the direction of Single
Frame Synchronization Pulse (TxSync), Multi-frame Synchronization Pulse
(TxMSync) and Transmit Serial Clock Input (TxSerClk). When the framer is
operating at other Back-plane mode, the Single Frame Synchronization Pulse
(TxSync), Multi-frame Synchronization Pulse (TxMSync) and Transmit Serial
Clock Input (TxSerClk) are all inputs.
00 - The Recovered Receive Line Clock is the timing source of Transmit section
of the framer. When operating at the non-multiplexed 2.048MHz Back-plane
Interface mode, the Single Frame Synchronization Pulse (TxSync), Multi-frame
Synchronization Pulse (TxMSync) and Transmit Serial Clock Input (TxSerClk)
are all outputs. Upon losing of the Recovered Receiver Line Clock, the OSCCLK
Driven Divided clock is automatically chosen to be the timing source of the
Transmit section of the framer.
01 - The Transmit Serial Clock is the timing source of Transmit section of the
framer. When operating at the non-multiplexed 2.048MHz Back-plane Interface
mode, the Single Frame Synchronization Pulse (TxSync), Multi-frame Synchro-
nization Pulse (TxMSync) and Transmit Serial Clock Input (TxSerClk) are all
inputs.
10 - The OSCCLK Driven Divided clock is the timing source of Transmit section
of the framer. When operating at the non-multiplexed 2.048MHz Back-plane
Interface mode, the Single Frame Synchronization Pulse (TxSync), Multi-frame
Synchronization Pulse (TxMSync) and Transmit Serial Clock Input (TxSerClk)
are all outputs. Upon losing of the Recovered Receiver Line Clock, the OSCCLK
Driven Divided clock is automatically chosen to be the timing source of the
Transmit section of the framer.
11 - The Recovered Receive Line Clock is the timing source of Transmit section
of the framer. When operating at the non-multiplexed 2.048MHz Back-plane
Interface mode, the Single Frame Synchronization Pulse (TxSync), Multi-frame
Synchronization Pulse (TxMSync) and Transmit Serial Clock Input (TxSerClk)
are all outputs. Upon losing of the Recovered Receiver Line Clock, the OSCCLK
Driven Divided clock is automatically chosen to be the timing source of the
Transmit section of the framer.
248
B
IT
D
ESCRIPTION
REV. 1.0.1