XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 8

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XRT84L38IB

Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet

Specifications of XRT84L38IB

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
XRT84L38
OCTAL T1/E1/J1 FRAMER
5.0 THE DS1 RECEIVE SECTION ............................................................................................................. 214
F
N
E
T
F
T
T
F
S
F
N
E
T
F
T
T
F
S
R
S
S
R
S
FIFO L
R
R
R
IRST
HIRTEENTH
IFTEENTH
ENTH
WELFTH
OURTEENTH
IRST
HIRTEENTH
IFTEENTH
ENTH
WELFTH
OURTEENTH
LEVENTH
IXTEENTH
LEVENTH
IXTEENTH
LIP
LIP
LIP
INTH
INTH
5.1 THE DS1 RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ......................................................... 214
ECEIVE
ECEIVE
ECEIVE
ECEIVE
ECEIVE
F
F
F
F
F
T
T
F
F
F
F
F
F
T
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
B
B
B
5.1.1 DESCRIPTION OF THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK............................................. 214
5.1.2 THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK OPERATING AT 1.544MBIT/S MODE .............. 214
5.1.3 HIGH SPEED RECEIVE BACK-PLANE INTERFACE................................................................................................ 225
O
O
O
O
UFFER
UFFER
UFFER
O
O
ATENCY
CTET OF
CTET OF
CTET OF
CTET OF
42: T
44: R
CTET OF
CTET OF
43: T
I
I
I
M
M
43. I
44. W
46. W
48. W
38. T
O
39. I
40. T
O
41. I
42. T
NTERFACE
NTERFACE
45. I
47. I
NTERFACE
4.1.3.6 T1 T
4.1.3.7 T1 T
5.1.2.1 C
5.1.2.2 C
5.1.2.3 C
O
O
ULTIPLEX
ULTIPLEX
O
O
O
O
CTET OF
CTET OF
216
AS
E
S
NAL
NAL
I
NTERFACE DATA RATES
CTET OF
O
CTET OF
O
CTET OF
CTET OF
HE
QUIPMENT WHEN THE
ECTION
HE
CTET OF
CTET OF
NTERFACING
NTERFACING
NTERFACING
C
C
S
NTERFACING
NTERFACING
ECEIVE
O
O
IMING
IMING
IMING
B
B
B
R
AVEFORMS OF THE
CTET OF
CTET OF
AVEFORMS OF THE
AVEFORMS OF THE
TATUS
ONTROL
ONTROL
E
E
CTET OF
CTET OF
R
R
R
UFFER IS BYPASSED
ECEIVE
UFFER IS ENABLED
UFFER IS CONFIGURED AS
QUIPMENT WHEN THE
QUIPMENT WHEN THE
16.384M
16.384M
ECEIVE
X
EGISTER
16.384M
16.384M
16.384M
16.384M
ONNECT THE
ONNECT THE
ONNECT THE
TS
D
D
D
..................................................................................................................................................................... 220
M
IAGRAM OF THE
RANSMIT
IAGRAM OF THE
RANSMIT
IAGRAM OF THE
16.384M
16.384M
C
C
B
C
E
E
ULTIPLEX
16.384M
16.384M
[2:0]
T
16.384M
16.384M
R
16.384M
16.384M
ONTROL
ONTROL
ONTROL
NABLE
NABLE
IMING
S
16.384M
16.384M
EGISTER
XRT84L38
XRT84L38
XRT84L38
R
R
XRT84L38
XRT84L38
ERIAL
16.384M
16.384M
EGISTER
EGISTER
BITS WHEN THE
BIT
BIT
(FIFOLR) (I
BIT
BIT
BIT
BIT
I
I
S
NPUT
NPUT
R
R
R
E
C
OURCE
/
/
B
B
S
/
/
BIT
BIT
ECEIVE
ECEIVE
S
ECEIVE
S
S
S
/
/
NABLE BIT AND
S
S
S
LOCK AND
BIT
S
BIT
S
IGNALS
IT
IT
............................................................................................................................................... 220
R
R
IGNALS THAT
IGNALS THAT
R
BIT
BIT
............................................................................................................................................... 226
BIT
BIT
LIP
D
D
............................................................................................................................................. 218
D
D
D
/
D
/
EGISTER
EGISTER
(SBSR) (I
EGISTER
BIT
BIT
I
I
I
I
I
= 0......................................................................................................... 226
= 1......................................................................................................... 227
S
S
LOCAL
TO THE
TO THE
TO LOCAL
TO LOCAL
NPUT
NTERFACE
ATA
NPUT
NTERFACE
ATA
NPUT
BIT
BIT
ATA
/
ATA
/
S
S
/
/
ATA
ATA
S
/
S
/
B
(SBCR) (I
(SBCR) (I
S
S
S
S
....................................................................................................................................... 219
LIP
LIP
D
D
UFFER IS
/
/
P
P
P
D
S
D
S
/
/
FIFO ........................................................................................................................... 223
D
D
C
ATA
ATA
D
D
AYLOAD
AYLOAD
AYLOAD
S
S
S
S
B
B
ATA
ATA
ONNECTING THE
S
S
D
S
S
D
S
ATA
ATA
R
S
ATA
S
ATA
R
T
UFFER IS
NDIRECT
UFFER IS ACTED AS
D
D
TREAM
TREAM
IGNALS TO THE
L
IGNALS TO THE
L
IGNALS TO THE
TREAM
TREAM
ECEIVE
ERMINAL
ATA
ATA
ECEIVE
TREAM
TREAM
OCAL
OCAL
ATA
ATA
S
S
T
C
T
C
(RICR) (I
(RICR) (I
(RICR) (I
R
- HMVIP 16.384M
- H.100 16.384M
S
S
ERMINAL
ERMINAL
S
S
TREAM
S
TREAM
S
ONNECT THE
ONNECT THE
ECEIVE
B
NDIRECT
TREAM
TREAM
D
D
D
S
TREAM
S
TREAM
TREAM
TREAM
YPASSED AND THE
S
T
S
T
ATA
ATA
ATA
NDIRECT
NDIRECT
F
TREAM
TREAM
S
.......................................................................................... 206
ERMINAL
.......................................................................................... 210
ERMINAL
E
TREAM
TREAM
......................................................................................... 206
......................................................................................... 207
......................................................................................... 210
......................................................................................... 211
RACTIONAL
E
INGLE
NABLED
A
QUIPMENT WITH
O
O
O
I
NTERFACE
..................................................................................... 207
..................................................................................... 211
DDRESS
E
E
UTPUT
UTPUT
UTPUT
................................................................................... 207
................................................................................... 207
................................................................................... 211
................................................................................... 211
R
QUIPMENT WITH
QUIPMENT WITH
F
.................................................................................. 208
F
.................................................................................. 212
F
NDIRECT
NDIRECT
NDIRECT
-F
ECEIVE
A
RAMER WHEN RUNNING AT
RAMER WHEN RUNNING AT
RAMER WHEN RUNNING AT
................................................................................ 207
................................................................................ 211
R
R
............................................................................... 207
............................................................................... 211
E
E
RAME
IV
DDRESS
................................................................................................... 223
A
A
ECEIVE
ECEIVE
QUIPMENT USING
QUIPMENT USING
FIFO......................................................................................... 225
I
I
I
DDRESS
DDRESS
T1 O
BIT
NTERFACE BLOCK TO THE
NTERFACE BLOCK TO THE
NTERFACE BLOCK TO THE
BIT
= 0
M
P
S
/
S
R
/
AYLOAD
ODE
YNCHRONIZATION SIGNALS FOR DIFFERENT
S
....................................................................................... 209
UTPUT BIT IS SET TO DIFFERENT VALUES
A
A
ECOVERED
P
P
A
S
..................................................................................... 205
XN
AYLOAD
AYLOAD
DDRESS
DDRESS
DDRESS
LIP
= 0
S
S
S
0H, 0
= 0
= 0
ELECT
B
LIP
LIP
XN
D
UFFER
ATA
XN
XN
B
B
AH, 0
D
D
HMVIP 16.384M
H.100 16.384M
UFFER
UFFER
L
X
ATA
ATA
[1:0]
0H, 0
0H, 0
INE
= 0
= 0
O
= 0
17H) ............................................ 223
B
UTPUT
YPASSED AND
O
O
C
B
HMVIP 16.384M
H.100 16.384M
BITS WITH THE RESULTING
XN
XN
XN
X
E
UTPUT
E
UTPUT
LOCK IS THE
IT
08H) ..................................... 221
X
X
NABLED OR
NABLED OR
-M
0H, 0
0H, 0
0H, 0
L
L
L
16H) .................................. 215
16H) .................................. 215
I
OCAL
NTERFACE BLOCK TO THE LOCAL
OCAL
OCAL
ULTIPLEXED
I
I
NTERFACE BLOCK TO THE LOCAL
NTERFACE BLOCK TO THE LOCAL
BIT
X
X
X
BIT
T
T
T
22H)......................... 214
22H)......................... 217
22H)......................... 225
/
ERMINAL
ERMINAL
ERMINAL
S
R
/
T
S
A
A
ECOVERED
D
IMING
CTS AS
CTS AS
D
BIT
ATA
BIT
ATA
16.384M
/
S
/
S
B
M
S
B
E
E
E
US
M
OURCE OF THE
ODE
.......................... 218
FIFO ................ 222
FIFO ................ 224
QUIPMENT IF THE
QUIPMENT IF THE
QUIPMENT IF THE
US
S
ODE
...................... 213
R
LIP
R
.................... 209
ECEIVE
ECEIVE
BIT
.................. 213
B
................ 209
UFFER SETTINGS
/
S
M
B
REV. 1.0.1
L
ODE
ACK
INE
T
R
ERMINAL
ECEIVE
C
-
T
T
PLANE
205
S
S
S
LOCK
ERMI
ERMI
LIP
LIP
LIP
-
-

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