HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet
HFIXF1110CC.B2 Q E000
Specifications of HFIXF1110CC.B2 Q E000
Related parts for HFIXF1110CC.B2 Q E000
HFIXF1110CC.B2 Q E000 Summary of contents
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... The integration of the SerDes functionality reduces PCB real- estate and system-cost requirements. Applications ® In general, the Intel IXF11101000 Mbps Ethernet Media Access Controller (called hereafter the IXF1110 MAC) is appropriate for high-end switching applications where MAC and SerDes functions are not integrated into the system ASIC. ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... Start-Up Parameters .............................................................................................. 64 5.2.2.1 CALENDAR_LEN .................................................................................. 64 5.2.2.2 CALENDAR_M ...................................................................................... 65 5.2.2.3 DIP2_Thr................................................................................................ 65 5.2.2.4 Loss_Of_Sync........................................................................................ 65 5.2.2.5 DATA_MAX_T ....................................................................................... 65 5.2.2.6 REP_T ................................................................................................... 65 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 07-Oct-2005 3 ...
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... General Description ............................................................................................... 88 5.6.2 Functional Description ........................................................................................... 89 5.6.2.1 Read Access.......................................................................................... 90 5.6.2.2 Write Access .......................................................................................... 91 5.6.2.3 Timing parameters ................................................................................. 92 5.6.3 Endian.................................................................................................................... 92 5.7 JTAG (Boundary Scan)....................................................................................................... 92 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 4 C Protocol Specifics ............................................................................ 79 Order Number: 250210, Revision: 009 Datasheet ...
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... SerDes Timing Specification............................................................................................. 119 7.10 SPI4-2 Timing Specifications ............................................................................................ 121 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 2 C Timing Specification ..................................................... 114 Order Number: 250210, Revision: 009 07-Oct-2005 5 ...
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... Acknowledge Timing .................................................................................................................. 81 19 Random Read ............................................................................................................................ 82 20 Byte Write ................................................................................................................................... 83 21 Mode 0 Timing ............................................................................................................................ 85 22 Mode 1 Timing ............................................................................................................................ 86 23 CPU Interface Inputs/Outputs..................................................................................................... 89 24 Read Timing – Asynchronous Interface ..................................................................................... 91 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 6 Order Number: 250210, Revision: 009 Datasheet ...
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... SerDes Driver TX Power Levels .................................................................................................72 22 IXF1110-to-SFP Connections..................................................................................................... 74 23 LED Signal Descriptions ............................................................................................................. 84 24 Mode 0 Clock Cycle to Data Bit Relationship ............................................................................. 85 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 07-Oct-2005 7 ...
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... RX Config Word ($ Port_Index + 0x16) ................................................................................... 136 72 TX Config Word ($ Port_Index + 0x17) .................................................................................... 137 73 Diverse Config ($ Port_Index + 0x18) ..................................................................................... 138 74 RX Packet Filter Control ($ Port_Index + 0x19) ....................................................................... 139 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 8 Order Number: 250210, Revision: 009 Datasheet ...
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... C Control Ports 0-9 ($ 0x79B) ...............................................................................................177 2 111 I C Data Ports 0-9 ($ 0x79C).................................................................................................... 178 112 Product Ordering Information ................................................................................................... 183 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 07-Oct-2005 9 ...
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... Added Section 6.3.1.3, “TX FIFO Drain (IXF1110 Version)”. 110 Added Table 48 “SPI4-2 LVDS Rise/Fall Times”. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 10 Revision Number: 009 Revision Date: 07-Oct-2005 Description Changed Standard to 3.3 V LVTTL from 2.5 V CMOS Table 11 “ ...
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... Changed Table 98: TX FIFO Port Reset Register (Addr: 0x620) to Reserved. Page # Added product ordering and operating temperature range information, and changed SFF-8053, 1 Revision 5.5 Compatible to SFP MSA compatible. Deleted old Figures 6, 7, and 8 (Revision 004) and replaced with Figure 6 “Intel 17 CBGA Assignments (Top View)” Added new Section 3.1, “Intel 18 in Alphanumeric Order by Signal Name” ...
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... Added note to “UPX_RDY” under Section 5.8.2, “Functional Description”. 95 Added note under Section 6.2.1, “TX FIFO”. 95 Added note under Section 6.2.1.1, “MAC Transfer Threshold”. 104 Modified/added Power Consumption Max to Table 49 “Intel 105 Modified Table 36 “Intel 105 Added Section 7.2, “Undershoot/Overshoot Specifications”. 107 Modified Table 39 “ ...
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... Added Table 107 “SerDes Tx Driver Power Level Ports 7-9 Register (Addr: 0x785)”. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Revision Number: 005 (Sheet Revision Date: November 24, 2003 Description Order Number: 250210, Revision: 009 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 1.0 Introduction This document describes the functionality and operation of the Intel Ethernet Media Access Controller. 1.1 What You Will Find in This Document This document contains the following sections: • Section 2.0, “General Description” on page 16 IXF1110 MAC block diagram system architecture. • ...
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... SPI4 Phase 2 Performance in Gigabit Ethernet Media Access Controllers Application Note Interfacing with the Intel Controllers Application Note ® Intel IXF1110 Thermal Design Considerations Application Note Flow Control in the Intel Controllers Application Note Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® ...
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... IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 2.0 General Description ® The Intel IXF1110 MAC is a 10-port 1000 Mbps Ethernet Media Access Controller (MAC). The 10 Gigabit interface to the network processor is supported through a System Packet Interface Level 4 Phase 2 (SPI4-2), and the media interface is an integrated Serializer/Deserializer (SerDes). ...
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... Figure 2. IXF1110 MAC System Block Diagram LED Serial-to-Parallel Converter Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Forwarding Engine Network Processor SPI4-2 IXF1110 LED Serial Interface SerDes/Optical Module Interface § ...
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... W20 V20 21 AD21 AC21 AB21 AA21 Y21 W21 V21 22 AD22 AC22 AB22 AA22 Y22 W22 V22 23 AD23 AC23 AB23 AA23 Y23 W23 V23 24 AD24 AC24 AB24 AA24 Y24 W24 V24 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
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... Hex notation. A Register Address is indicated by the dollar sign ($), followed by the memory location in Hex. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 2 2 C_DATA_0, I C_DATA_1, etc. ...
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... IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 20 Table 1, “SPI4-2 Interface Signal Descriptions” TDAT[15:0]_P/N TDCLK_P/N TCTL_P/N TSTAT[1:0] TSCLK RDAT[15:0]_P/N RDCLK_P/N RCTL_P/N RSTAT[1:0] RSCLK ® TMS Intel TDI TDO IXF1110 TCLK TRST_L TXPAUSEADD[3:0] TXPAUSEFR UPX_DATA[31:0] UPX_ADD[10:0] UPX_WR_L UPX_RD_L UPX_CS_L UPX_RDY_L Order Number: 250210, Revision: 009 through Table 10, “ ...
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... TDAT2_P, TDAT2_N TDAT1_P, TDAT1_N TDAT0_P, TDAT0_N TDCLK_P TDCLK_N TCTL_P TCTL_N TSCLK TSTAT1 TSTAT0 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type Standard G11 H11 K10 ...
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... RDAT4_P, RDAT4_N RDAT3_P, RDAT3_N RDAT2_P, RDAT2_N- RDAT1_P, RDAT1_N RDAT0_P, RDAT0_N RDCLK_P RDCLK_N RCTL_P RCTL_N RSCLK RSTAT1 RSTAT0 07-Oct-2005 ® Intel IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 22 Ball Designator Type Standard K12 K13 F16 G16 E13 E14 A13 A14 J16 ...
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... RX_P_5, RX_N_5 RX_P_6, RX_N_6 RX_P_7, RX_N_7 RX_P_8, RX_N_8 RX_P_9, RX_N_9 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type Standard V20 V21 Y19 Y20 V22 W22 ...
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... UPX_DATA11 UPX_DATA10 UPX_DATA9 UPX_DATA8 UPX_DATA7 UPX_DATA6 UPX_DATA5 UPX_DATA4 UPX_DATA3 UPX_DATA2 UPX_DATA1 UPX_DATA0 1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode. 07-Oct-2005 ® Intel IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 24 Ball Designator Type Standard 2 Input CMOS ...
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... Pause Control Interface Signal Descriptions Signal Name TXPAUSEFR TXPAUSEADD3 TXPAUSEADD2 TXPAUSEADD1 TXPAUSEADD0 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type Standard 2.5 V A18 Input CMOS 2.5 V H14 Input ...
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... TX_DISABLE_3 TX_DISABLE_4 TX_DISABLE_5 TX_DISABLE_6 TX_DISABLE_7 TX_DISABLE_8 TX_DISABLE_9 TX_FAULT_INT 1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode. 07-Oct-2005 ® Intel IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 26 Ball Designator Type Standard M24 V23 Y17 R15 W14 2.5 V ...
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... Table 6. LED Interface Signal Descriptions Signal Name LED_CLK LED_DATA LED_LATCH Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type Standard Open 2.5 V B14 Drain CMOS Output* Open 2 ...
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... Signal Name TCK TMS TDI TRST_L TDO Table 8. System Interface Signal Descriptions Signal Name CLK125 CLK50 SYS_RES_L 07-Oct-2005 ® Intel IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 28 Ball Designator Type Standard 3.3 V AA24 Input LVTTL 3.3 V T16 Input LVTTL 3.3 V ...
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... Power Supply Signal Descriptions (Sheet Signal Name AVDD1P8_1 AVDD1P8_2 AVDD2P5_1 AVDD2P5_2 VDD VDD2 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type D1 E24 – P7 P18 V6 V11 – V14 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 9. Power Supply Signal Descriptions (Sheet Signal Name GND 07-Oct-2005 ® Intel IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 30 Ball Designator Type B6 B10 B15 B19 D12, D13 D17 D21 D22 ...
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... Table 10. Unused Balls/Reserved Signal Name NC No Ball No Pad Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type A5 A6 C10 C15 G7 G8 H22 J22 K7 L21 L23 M1 M7 ...
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... Ball list tables are provided in alphanumeric order by signal name order (Table 12). Note: Intel recommends that all unconnected balls be tied to their inactive states through external pull-ups or pull-downs. 4.3.1 Balls Listed in Alphanumeric Order by Signal Name Table 11 shows the ball locations and signal names arranged in alphanumeric order by signal name. ...
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... GND GND GND GND GND GND GND GND GND GND Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Signal Ball P15 GND W3 P21 GND W5 P23 GND W6 P24 ...
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... IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Signal 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 34 Ball Signal Ball M7 NC AB22 N1 NC AD4 N5 NC AD5 N7 NC AD6 N20 NC AD7 P4 NC AD8 P5 NC AD17 P6 NC AD19 P17 NC AD20 P19 No Ball A2 P20 No Ball Ball A22 R13 ...
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... TDAT0_N TDAT0_P TDAT1_N TDAT1_P TDAT2_P TDAT3_N TDAT3_P TDAT4_N TDAT4_P TDAT5_N Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Signal Ball Y9 TDAT5_P G5 AC3 TDAT6_N L7 T2 TDAT6_P L8 P2 TDAT7_N ...
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... UPX_DATA10 UPX_DATA11 UPX_DATA12 UPX_DATA13 UPX_DATA14 UPX_DATA15 UPX_DATA16 UPX_DATA17 UPX_DATA18 UPX_DATA19 UPX_DATA20 UPX_DATA21 UPX_DATA22 UPX_DATA23 UPX_DATA24 UPX_DATA25 UPX_DATA26 UPX_DATA27 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 36 Ball Signal Ball F3 UPX_DATA28 B18 H1 UPX_DATA29 A21 E3 UPX_DATA30 B22 E2 UPX_DATA31 C23 G1 UPX_RD_L ...
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... VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball N9 N12 N13 N16 N19 N23 T12 T13 U2 U6 U19 U23 ...
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... Balls Listed in Alphanumeric Order by Ball Location Table 12 shows the ball locations and signal names arranged in alphanumeric order by ball location. Note: Intel recommends that all unconnected balls be tied to their inactive states through external pull- ups or pull-downs. Table 12. Ball List in Alphanumeric Order by Ball Location Ball Signal ...
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... F12 VDD2 F13 VDD2 F14 UPX_DATA18 F15 GND Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Signal F16 RDAT14_P F17 VDD2 F18 RDAT2_P F19 GND F20 UPX_CS_L ...
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... GND L4 TX_DISABLE_9 L5 TDAT8_P L6 GND L7 TDAT6_N L8 TDAT6_P L9 VDD L10 GND L11 VDD L12 GND 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 40 Ball Signal L13 GND L14 VDD L15 GND L16 VDD L17 RDAT5_P L18 RDAT5_N 2 L19 I C_CLK L20 ...
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... MOD_DEF_6 T5 TX_P_9 GND T8 GND T9 GND Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Signal T10 GND T11 VDD T12 VDD2 T13 VDD2 T14 VDD T15 GND T16 ...
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... Y23 TX_P_3 Y24 TDO AA1 GND AA2 VDD2 AA3 GND AA4 GND AA5 CLK125 AA6 VDD 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 42 Ball Signal AA7 GND AA8 GND AA9 TX_DISABLE_7 AA10 VDD AA11 NC AA12 GND AA13 ...
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... RX_P_7 AD17 NC AD18 RX_LOS_2 AD19 NC AD20 NC AD21 GND AD22 No Ball AD23 No Ball AD24 No Ball Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 07-Oct-2005 43 ...
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... SPI4-2 interface and automatically padded bytes by the MAC. This feature is enabled by setting bit 7 of the “Diverse Config ($ Port_Index + 0x18)” on page 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 44 cover the MAC functions. Order Number: 250210, Revision: 009 through Section 5 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 74, “RX Packet Filter Control ($ 139, are sent across the SPI4-2 interface as an EOP abort frame. Table 74, “RX Packet Filter Control ($ ...
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... Any packet (Pause, Unicast, Multicast or Broadcast packet) with a CRC error will be marked as a bad frame when the CRC Error Pass Filter bit = 0. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 46 “RX Packet Filter Control ($ Port_Index + 0x19)” ...
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... IEEE 802.3 FIFO flow control functions. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Frame Drop En Packets are passed to the SPI4-2 interface. They are not 0 marked as bad and are sent to the switch or Network Processor ...
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... Figure 6. Ethernet Frame Format Number of bytes Preamble 64 yte Minimum / 1518 bytes Maximum Note: 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 48 TX FIFO Data Flow Data Flow RX FIFO RX FIFO High 802.3 Flow control 802 ...
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... Number of bytes Preamble ® Note: In the Intel IXF1110 architecture, the TX block of the MAC sets this as the pause multicast address. The RX interface of the MAC will process this as the pause multicast or the MAC address. An IEEE 802.3 MAC PAUSE frame is identified by detecting all of the following: • ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 50 through “Station Address High ($ Port_Index + Section 5.1.2.3.5, “Filter PAUSE Packets” on page 46 Figure 8, “Transmit Pause Control Interface” on page 51 Figure 8 “FC Enable ($ Port_Index + 0x12)” ...
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... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller TX Pause Control Interface Operation Transmits a PAUSE frame on port 5 with pause_time equal to the value programmed in the port 5 “FC TX Timer Value ($ Port_Index + 0x07)" ...
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... A valid link is established when the (AN_complete) bit is set and the RX_Sync bit reports synchronization has occurred. Both register bits are located in the + 0x16)”. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 52 137, “Diverse Config ($ Port_Index + 0x18)” on 0x18)”. When auto-negotiation is disabled, the IXF1110 can operate in ...
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... RXPkts1519toMaxOctets (Addr: Port_Index + 0x2B) Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller “Diverse Config ($ Port_Index + 0x18)” “RX Config Word ($ Port_Index + 0x16)” Order Number: 250210, Revision: 009 “Diverse Config ($ Port_Index + ...
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... RMON statistics is available for each MAC device in the IXF1110 MAC. Implementation of the RMON Statistics block is similar to the functionality provided by existing Intel switch and router products. This implementation allows the IXF1110 MAC to provide all of the RMON Statistics group as defined by RFC2819. ...
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... The IXF1110 MAC has an extra counter RX/TXPktstoMaxOctets that can be used in addition to the RMON stats. This is required to accommodate the Jumbo packet frames requirement. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller IXF1110 MAC Equivalent Type Statistics Integer32 N/A ...
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... Additional Statistics The following additional IXF1110 MAC registers support features not documented in RMON: • MAC (flow) control frames 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 56 IXF1110 MAC Equivalent Type Statistics TXSingleCollisions TXMultipleCollisions ...
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... However, if the invalid code is inserted in a byte position of less than 64, expected RX statistics are not stored. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 07-Oct-2005 57 ...
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... TDAT[15:0]_P/N Intel ® IXF1110 MAC RDAT[15:0]_P/N Table 17. SPI4-2 Interface Signal Summary (Sheet Signal Name TDAT[15:0]_P/N TDCLK_P/N TCTL_P/N 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 58 Figure 9 Transmit FIFO Status/ SPI-4.2 Flow Control Signals Transmit TSCLK Data TSTAT[1:0] Control ...
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... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Signal Description Transmit Status Clock: LVTTL clock associated with TSTAT [1:0]. Frequency is equal to one-quarter TDCLK. Transmit FIFO Status: LVTTL lines used to carry round-robin FIFO status information, along with associated error detection and framing ...
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... MSB is sent on the MSB of the transmit or receive data lines. A payload control word that separates two adjacent burst transfers contains status information pertaining to the previous transfer and the following transfer. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 60 Table 19 provides a list of control-word definitions. ...
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... Valid Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Control Word Type. Set to either of the following values Idle or training control word 1 = Payload control word (payload transfer will immediately follow the control word) End-of-Packet (EOP) Status ...
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... EOP Aborts is an End-of-Packet (EOP) termination that is sent out of the IXF1110 MAC SPI4-2 to tell the upstream SPI4-2 device that a packet is bad. EOP Abort packets are sent by the IXF1110 MAC under the following conditions: 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 62 Prior Word Status EOP w/ 2 bytes ...
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... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (“RX Packet Filter Control ($ Port_Index “RX FIFO Errored Frame Drop Enable ($ and are not dropped due to the setting in the 0x59F)”. ...
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... Figure 13. DIP-4 Calculation Algorithm 5.2.2 Start-Up Parameters 5.2.2.1 CALENDAR_LEN CALENDAR_LEN specifies the length of each calendar sequence. As the IXF1110IXF1110 MAC is a 10-port device, CALENDAR_LEN is fixed at 10 for both TX and RX data paths. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
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... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 174, bits specify this parameter. The 174, bits specify this parameter. The default Table 102, “SPI4-2 RX Training ($ 0x701)” on page Table 102, “ ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 66 Table 101, “SPI4-2 RX Burst Size ($ 0x700)” on Table 101, “SPI4-2 RX Burst Size ($ 0x700)” on page Order Number: 250210, Revision: 009 175, bits specify this parameter ...
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... CALENDAR_M times, followed by the DIP-2 code. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 173). This is done when a system shows very little drift Order Number: 250210, Revision: 009 Table 102, 07-Oct-2005 ...
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... The “1 1” framing pattern is not included in the parity calculation. The procedure described applies to either parity generation on the egress path or to check parity on the ingress path. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 68 SYNC 11 Port 0 ...
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... When a repeated “1 1” pattern is detected, all outstanding credits are cancelled and set to zero. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 0 1 Framing Pattern (not included 1 ...
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... During data transfers where each of the data transfers (MaxBurst1 or MaxBurst2) are separated by more than one idle control word 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 70 Description Table 104, “SPI4-2 TX Synchronization ($ 0x703)” on page Order Number: 250210, Revision: 009 175 ...
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... Asynchronous clock data recovery Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 36, “2.5 V LVTTL and CMOS I/ and Table 37, “LVDS I/O Electrical Characteristics” on “Fiber Operation” on page “ ...
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... Normalized Driver Power Setting column are multiples of 10 mA. For example, with inputs at 1110, the driver power mA. Table 21. SerDes Driver TX Power Levels DRVPWRx[3] DRVPWRx[ NOTE: All other values are reserved. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 72 differential terminated network, these output power set- DRVPWRx[1] DRVPWRx[ ...
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... IXF1110-to-SFP optical module connection pins. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller “SerDes TX and RX Power-Down Ports 0-9 ($ 0x787)” on and Section 8.5.9, “Optical Module Interface Block Register 177). ...
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... MOD_DEF_9:0 • TX_FAULT_9:0 • RX_LOS_9:0 • TX_DISABLE_9:0 • MOD_DEF_Int • TX_FAULT_Int • RX_LOS_Int 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 74 SFP Module Description Pin Name TD+ Transmit Data, Differential SerDes TD- RD+ Receive Data, Differential SerDes RD- 2 MOD-DEF1 I C_CLK Output from IXF1110 (SCL) ...
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... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller “Optical Module Status Ports 0-9 ($ 0x799)” “Optical Module Control Ports 0-9 ($ takes place. The signal then returns to an Order Number: 250210, Revision: 009 177) ...
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... Ten per-port I requirement that all modules must be addressed as 00h. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 76 Table 108, “Optical Module Status Ports 0-9 ($ 0x799)” on Table 108, “Optical Module Status Ports 0-9 ($ 0x799)” on Table 108, “Optical Module Status Ports 0-9 ($ 0x799)” on ...
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... C access. In addition the Write Protect Error bit will be set to indicate a write has been initiated to the write protected optical module. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 2 C interface is controlled through separate Prom family. I ...
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... Set the 11-bit Register Address, bits [10:0] to 0xFF. f. Initiate the I All other bits in this register should be written with the value ‘0’. This data is written into the I 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Control Ports 0-9 ($ 0x79B)” on page 177 2 C transfer by setting bit 24 to ‘ ...
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... C_CLK Low time periods (see periods indicate a start or stop condition. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 2 C Start bit Logic 1, the I 2 C_DATA_0:9 output for the selected port Protocol Specifics” ...
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... Acknowledge All addresses and data words are serially transmitted to and from the optical module in 8-bit words. The optical module E happens during the ninth clock cycle (see 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 80 DATA STABLE DATA CHANGE ...
Page 81
... A random Read requires a “dummy” Byte/Write sequence to load the data word address. The following describes how to achieve the “dummy” Write: Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller START 2 C_CLK is High 2 PROM returns to a standby state. ...
Page 82
... The optical module acknowledges receipt of the data word address. • The IXF1110 sends the data byte to be written. • The optical module acknowledges the data word. • The IXF1110 generates a stop condition (see 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
Page 83
... Mode selection is accomplished by using bit 0 of the bit is globally selected and controls the mode of operation of all ports 5.5.2.2 provide the two modes of operation. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller WORD DEVICE T ADDRESS ...
Page 84
... LED_CLK, which is used to clock the data into the M5450 device.The actual data shown in LED DATA. The 36-bit data chain is built up as follows: 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (default). “LED Control ($ 0x509)” ...
Page 85
... LED_LATCH signal is active High during the Low period on the 36th LED_CLK cycle. This avoids any possibility of trying to latch data shifting through the register. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
Page 86
... This enables the per-port link LEDs for the IXF1110 MAC. Link LEDs do not automatically update. For more details on which LEDs are affected by this register, refer to section Section 5.5.7.1, “LED Signaling Behavior” on page 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
Page 87
... The operation in each mode for the decoded LED data in Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller IXF1110 Designation # Rx LED - Amber 0 Rx LED - Green Tx LED - Green Rx LED - Amber ...
Page 88
... SerDes Block • Optical Module Block Figure 23 illustrates the I/O for the CPU interface on the IXF1110 MAC. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 88 Status Synchronization has occurred but no packets are being received and Off set. ...
Page 89
... CPU interface. This address must be stable for the entire cycle. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 32 11 Figure 24, “Read Timing – Asynchronous Interface” on page Direction ...
Page 90
... IXF1110 MAC asserts asynchronous-ready (UPX_RDY_L). This indicates to the CPU that the Read cycle is complete. Figure 24 provides the timing of the asynchronous interface for Read access. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 90 Order Number: 250210, Revision: 009 Datasheet ...
Page 91
... Figure 25. Write Timing – Asynchronous Interface UPX_ADD[10:0] UPX_CS_L UPX_WR_L UPX_DATA[31:0] UPX_RDY_L Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Tcas Tcdrs Tcdrh T CAS T CWL T CDWS Order Number: 250210, Revision: 009 ...
Page 92
... JTAG (Boundary Scan) The IXF1110 MAC includes an IEEE 1149.1 boundary scan test port for board level testing. All inputs are accessible. The BSDL file for this device is available by accessing the intel website developer.intel.com. 5.7.1 TAP Interface (JTAG) The IXF1110 MAC includess an IEEE 1149 ...
Page 93
... The ID register is a 32-bit register. The IDCODE instruction connects this register between TDI and TDO. Refer toTable 87, “JTAG ID Revision ($ 0x50C)” on page 153 descriptions. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller resistor resistor resistor Code Description 0000 External Test ...
Page 94
... Maximum duty cycle distortion 45/55 • Maximum peak-to-peak jitter (low and high frequency) of 125 pS • Range = 40 Mhz to 50 MHz 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 94 2 output clock, and an LED output clock Order Number: 250210, Revision: 009 Section 5 ...
Page 95
... Maximum frequency of 720 Hz • Maximum duty cycle distortion: 50/50 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 2 clock to support all 10 optical module interfaces Order Number: 250210, Revision: 009 07-Oct-2005 ...
Page 96
... AVDD1P8_2) supplies by more than 2.0 V during power-down, damage can occur to the ESD structures within the analog I/Os. Figure 26. Power Sequencing t=0 Apply VDD, AVDD1P8_1/ AVDD1P8_2 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 96 provide information on power sequencing. 2.5 V Supplies Stable 1.8 V Supplies Stable Apply VDD2, AVDD2P5_1/ AVDD2P5_2 ...
Page 97
... The IXF1110 MAC packet buffering is comprised of individual port FIFOs and system-interface FIFOs. Figure 28 illustrates the interaction of these FIFOs. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Time Delta to Next Power-Up Order 1 Supply First 0 Second ...
Page 98
... TX FIFO exceeds the MAC transfer threshold, it will start to be transmitted to the MAC. If the MAC transfer is greater than the packet size, the packet is sent to the MAC once an EOP is received. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 98 TX FIFO Data Flow ...
Page 99
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 94, “TX FIFO High Watermark Ports 0 163. If the MAC transfer threshold is set above the TX FIFO high “TX FIFO High Watermark Ports 0x600 - 0x613)” ...
Page 100
... Pause control frame generation is enabled by default in the Section 8.5.5, “Global RX Block Register Overview” on page 154 to set the RX FIFO watermarks. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 100 “FC Enable ($ Port_Index + Order Number: 250210, Revision: 009 0x12)”. ...
Page 101
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller settings. The data is marked with an EOP abort code to inform the “SPI4-2 RX Calendar ($ 0x702)” Order Number: 250210, Revision: 009 “RX FIFO Errored Frame is “ ...
Page 102
... Power-down “SerDes TX and RX Power-Down Ports 0-9 ($ 0x787)” 3. The SerDes port is now powered down and the TSAT Status for the port is SATISFIED 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 102 “Dynamic Phase Alignment Training Sequence 66. “SPI4-2 RX Calendar ($ 0x702)” on page 174 must be set. A link is established when the RX SerDes has received the “ ...
Page 103
... IXF1110 MAC Unused Ports Intel recommends the following be used to disable an unused port. The SPI4-2 TSTAT status bus will always reflect status for ten ports regardless of the number of IXF1110 MAC unused ports. Any port which is disabled will have a constant status of SATISFIED. RSTAT must also be input to reflect the status of all ten ports regardless of how many are disabled ...
Page 104
... TxFault 3 TxDisable MOD_DEF 4 (2) MOD_DEF 5 (1) MOD_DEF 6 (0) 7 Rate Select NA 8 LOS 9 VeeR 10 VeeR 11 VeeR 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 104 VDD 3.3 V 4.7 k 4.7 k 4.7 k 4 TXFault 4 MOD_DEF(2) 5 MOD_DEF(1) 6 MOD_DEF(0) 8 LOS 3 TXDisable 18 TD+ 19 ...
Page 105
... N/A N/A N/A Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller IXF1110 Pin # 0:9 IXF1110 Pin Name U22, U20, T24, V24, AB14, AD14, AC16, RX_N_[0:9] AD15, V4, Y5 T22, T20, U24, W24, ...
Page 106
... Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 106 and Figure 30 on page 110 2 C Timing Specification” ...
Page 107
... Operating Current Recommended Operating Temperature Recommended Storage Temperature Power Consumption 1. Typical values are at 25 testing. 2. Refer to the Intel® IXF1110 Thermal Design Guidelines (document number 250289). Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
Page 108
... Output High Voltage Differential Output Voltage Delta Differential Output Voltage (Complementary States) Offset (Common- Mode) Voltage Output Leakage Current 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 108 1 Symbol Min Typ Max V – – 0. 1.7 – ...
Page 109
... Exceeding these values will damage the device. Table 38. Undershoot/Overshoot Limits Ball Type 2.5 V CMOS 2.5 V LVTTL Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 38). Undershoot Overshoot -0.60 V 3.9 V -0.60 V 3.9 V ...
Page 110
... Table 39. CPU Timing Parameters (Sheet Parameter UPX_ADD[12:0], UPX_CS_L Setup Time UPX_ADD[12:0], UPX_CS_L Hold Time UPX_RDY_L Assertion to UPX_RD_L De-assertion 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 110 T CAS T CDRS T CDRD T CAS T CWL ...
Page 111
... Read UPX_RDY_L de-assertion to UPX_WR_L Assertion Write UPX_RDY_L de-assertion to UPX_RD_L Assertion 1. Typical values are at 25 testing. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Symbol Min 24 T CRH (3x cycle CDRS ...
Page 112
... TCLK High Time TCLK Low Time TCLK Falling Edge to TDO Valid TMS/TDI Setup to TCLK TMS/TDI Hold from TCLK 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 112 Tjc Tjl Tjh Tjval Tjsh Tjsu 1 Symbol Min ...
Page 113
... TXPAUSEADDR[3:0] Hold from TXPAUSEFR TXPAUSEFR Pulse to Pulse 1. Typical values are at 25 testing. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Tbtp Tpw Tsu Thd 1 Symbol Min Typ Max T 16 – ...
Page 114
... Table 42. Optical Module Interrupt Timing Parameters Parameter Change of state on MOD_DEF_9:0 or TX_FAULT_9:0 or RX_LOS_9:0 to assertion (active Low) on MOD_DEF_Int or TX_FAULT_Int or RX_LOS_Int 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 114 2 C Timing Specification Tdi 1 Symbol Min Typ T 24 – ...
Page 115
... Start Setup Time Data In Hold Time Data In Setup time Inputs Rise Time 1. Typical values are at 25 testing. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller t HIGH LOW LOW ...
Page 116
... Table 43 Timing Characteristics (Sheet Parameter Inputs Fall Time Stop Setup Time Data Out Hold Time Write Cycle Time 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 116 1 Symbol Min Typ t – – 4.7 – ...
Page 117
... Table 44. Hardware Reset Timing Parameters Parameter Reset Pulse Width Reset Recovery Time 1. Typical values are at 25 testing. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Trw 1 Symbol Min Typ Max T 100 – ...
Page 118
... LED_CLK Rising Edge to LED_LATCH Falling Edge LED_CLK Falling Edge to LED_LATCH Rising Edge 1. Typical values are at 25 testing. 2. Flash Rate = 100 ms, LED Mode 1. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 118 Tcyc Tlow Thi Tdatd 1 Symbol Min Typ ...
Page 119
... NOTE: Refer to Table 21, “SerDes Driver TX Power Levels” on page 72 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Figure 39 illustrates the timing requirements for the IXF1110 Rt Tt Normalized Power ...
Page 120
... Receive Eye Width Receiver termination impedance Signal detect level Total Receiver jitter tolerance 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 120 Normalized Power Symbol Min Typ Driver Setting – 1.00 ...
Page 121
... TSCLK Rising Edge to TSTAT[1:0] Valid (Default operation) 1. Typical values are at 25 testing. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Td1 Td2 1 Symbol Min Typ T 1 – ...
Page 122
... Typical values are at 25 testing. Table 50. SPI4-2 LVDS Rise/Fall Times Parameter Symbol Rise/Fall at RTsrc source Rise/Fall at sink RTsnk 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 122 Tsu1 Th1 Th2 Tsu2 1 Symbol Min Typ – ...
Page 123
... Do not write to any reserved register unless specified. Writing to a reserved register address may cause improper device operation. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 07-Oct-2005 123 ...
Page 124
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Figure 42. Memory Overview 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 124 Global Configuration -RX Block Configuration -TX Block Configuraiton Port 9 MAC Control & Statistics Port 8 MAC Control & Statistics Port 7 MAC Control & ...
Page 125
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 6 provide theIXF1110 MAC memory maps. A number of Register Bit Size MAC Control Registers (Port Index + Offset) ...
Page 126
... RXPkts1024to1518Octets RXPkts1519toMaxOctets RXFCSErrors RXTagged RXDataError Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 126 Register Bit Size MAC Control Registers (Port Index + Offset) Register Bit Size MAC RX Statistics Registers (Port Index + Offset) ...
Page 127
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Register Bit Size MAC RX Statistics Registers (Port Index + Offset) Register Bit Size ...
Page 128
... Flash Rate ($ 0x50A)” “LED Fault Disable ($ 0x50B)” “JTAG ID Revision ($ 0x50C)” Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 128 Register Bit Size MAC TX Statistics Registers (Port Index + Offset) ...
Page 129
... FIFO Overflow Event ($ 0x5A0)” Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Register Bit Size RX Block Registers Order Number: 250210, Revision: 009 Ref ...
Page 130
... FIFO Drain ($0x620)” “TX FIFO Info Out-of-Sequence ($ 0x621)” TX FIFO Number of Frames Removed on Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 130 Register Bit Size Order Number: 250210, Revision: 009 ...
Page 131
... Reserved Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Register Bit Size Register Bit Size Register Order Number: 250210, Revision: 009 ...
Page 132
... C Control Ports 0-9 ($ 0x79B)” 2 “I C Data Ports 0-9 ($ 0x79C)” Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 132 Register Bit Size Order Number: 250210, Revision: 009 Ref 1 ...
Page 133
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller provide details on the control and status registers associated Description Source MAC address bits 31-0. This address is inserted in the source address field ...
Page 134
... IPG Transmit 9:0 Time Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 134 Description Contains the value of the lowest 32 bits of the destination address field transmitted in an internally generated flow control (pause) frame. Internally ...
Page 135
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Reserved When a pause frame is sent, an internal timer checks when a new pause frame must be scheduled for transmission to keep the link partner in pause mode ...
Page 136
... RX Sync 19 RX Config Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 136 Description Reserved 0 = Disable TX full-duplex flow control [the MAC will not generate internally any flow control frames based on the RX FIFO watermarks or ...
Page 137
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description 0 = RxConfigWord has changed since last read 1 = RxConfigWord has not changed since last read (This bit remains High until register is read) ...
Page 138
... Reserved Read Only; CoR = Clear on Read Write; R/W = Read/Write 2. Reserved bits must be written to the default value for proper operation 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 138 (Sheet Description Ability to send and receive pause frames Half-duplex ...
Page 139
... SPI4-2 interface and marked as EOP abort frames. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Reserved This bit enables a Global filter on frames with a CRC Error. When CRCErrorPASS = 0, all frames with a CRC Error are marked as bad ...
Page 140
... Reserved Port Multicast 15:0 Address High Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 140 Description This bit enables a Global filter on Broadcast frames. When B/CastDropEn = 0, all broadcast frames are 2 passed to the SPI4-2 Interface. ...
Page 141
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Counts the bytes received in all legal frames, including all bytes from the destination MAC address to and including the CRC. The initial preamble and SFD bytes are not counted ...
Page 142
... LongErrors is incremented. This is due to a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD counter if the frame is larger than 2^14-1. MaxFrameSize is determined by the settings in the 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 142 Description The total number of packets received (including bad packets) that were [65-127] octets in length ...
Page 143
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Frames bigger than the maximum allowed, with both OK CRC and the integral number of octets Default maximum allowed is 1518 bytes ...
Page 144
... LongErrors is incremented. This is due to a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD counter if the frame is larger than 2^14-1. MaxFrameSize is determined by the settings in the 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 144 Description The total number of packets received that are ...
Page 145
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Counts the bytes transmitted in all legal frames. The count includes all bytes from the destination MAC address to and including the CRC ...
Page 146
... TXPkts1519toMaxOctets TXDeferred TXTotalCollisions TXSingleCollisions Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 146 Description The total number of packets transmitted (including bad packets) that were [128-255] octets in length. Incremented for tagged packets with a ...
Page 147
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description A count of successfully transmitted frames on a particular interface for which transmission is inhibited by more than one collision ...
Page 148
... TXCRCError TXPauseFrames TXFlowControlCollisions Send Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 148 Description Number of frames transmitted with a legal size, but with the wrong CRC field (also called FCS field) ...
Page 149
... If a port is disabled mid-packet on the receive side in SerDes mode, the RX Stats will not update for that packet due to power-down of SerDes when the port is disabled. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller provide an overview of the Global Control and Status Description Reserved Port Disable ...
Page 150
... Register Description : A soft reset register for the core clock system (for example, the SYS125 clock). 31:1 Reserved Core Soft 0 Reset Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 150 Description Reserved Port 9 link link 1 = Link Port 8 link link ...
Page 151
... Reserved 0 Endian Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Name Description Reserved Port Reset inactive 1 = Reset active Port Reset inactive ...
Page 152
... LED Fault 7 Disable Port 7 LED Fault 6 Disable Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 152 Name Description Reserved 0 = Disable LEDs 1 = Enable LEDs 0 = Enable LED Mode 0 for use with SGS ...
Page 153
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write 2. See the IXF1110 Specification Upate for the latest version. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Port Fault enabled 1 = Fault disabled Port 4 ...
Page 154
... For all RX FIFO High Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:15 - Reserved and R. Bits 14:0 - Described above. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 154 provide an overview of the RX Block Registers, which Description High watermark for RX FIFO port 0 ...
Page 155
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description High watermark for RX FIFO port 7. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC ...
Page 156
... For all RX FIFO Low Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:15 - Reserved and R. Bits 14:0 - Described above. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 156 Description Low watermark for RX FIFO port 5. The default value is 1840 bytes ...
Page 157
... Bits 21:0 - Described above. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description This register counts all frames removed from the RX FIFO for port 0 by meeting one of the following conditions: • ...
Page 158
... For all Number of Frames Removed Registers, the following bit definitions apply to all ports (0:9): Bits 31:22 - Reserved and R. Bits 21:0 - Described above. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 158 Description This register counts all frames removed from ...
Page 159
... RXFIFOPort 0 0 Reset Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Reserved Port De-assert reset 1 = Reset Port De-assert reset ...
Page 160
... Errored Frame 4 Drop Enable Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 160 Description Reserved These bits are used in conjunction with the Packet Filter Control ($ Port_Index + 0x19)” allowing the user to select whether errored or filtered frames are to be dropped or not ...
Page 161
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description These bits are used in conjunction with the Packet Filter Control ($ Port_Index + 0x19)” allowing the user to select whether errored or filtered frames are to be dropped or not ...
Page 162
... Event Port 1 RX FIFO Overflow 0 Event Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 162 Description Port FIFO overflow event did not occur 1 = FIFO overflow event occurred Port FIFO overflow event did not occur ...
Page 163
... Bits 31:13 - Reserved and R. Bits 12:0 - Described above. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller provide an overview of the TX Block Registers, which Order Number: 250210, Revision: 009 1 Address Type ...
Page 164
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write 2. For all TX FIFO Low Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 164 Order Number: 250210, Revision: 009 1 Address ...
Page 165
... For all TX FIFO Low Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 1 Address Type Default 0x60E ...
Page 166
... Bits 31:13 - Reserved and R. Bits 12:0 - Described above. 3. For proper operation of the IXF1110, the MAC transfer threshold must be set to greater than the MaxBurst1 on the SPI4-2. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 166 3 Order Number: 250210, Revision: 009 1 ...
Page 167
... For proper operation of the IXF1110, the MAC transfer threshold must be set to greater than the MaxBurst1 on the SPI4-2. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 3 Order Number: 250210, Revision: 009 1 Address Type ...
Page 168
... TX FIFO Overflow 9 Event Port 9 TX FIFO Overflow 8 Event Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 168 3 Description Reserved Port FIFO overflow event did not occur 1 = FIFO overflow event occurred ...
Page 169
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Port FIFO overflow event did not occur 1 = FIFO overflow event occurred ...
Page 170
... Sequence Port 7 TX FIFO Info 6 Out-of- Sequence Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 170 Description Port Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode Port Disable TX FIFO drain mode ...
Page 171
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Port FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred ...
Page 172
... TX FIFO Number of Frames Removed on Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 172 Description This register counts the number of frames removed on port 6 due FIFO overflow. This register counts the number of frames removed on port 7 due FIFO overflow ...
Page 173
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller provide an overview of the SPI4-2 Block Registers. Description 0 = Zero idle insertion between transfer bursts 1 = Inserts four idle control words between each burst ...
Page 174
... Loss_of_Sync 7:4 Reserved 3:0 Reserved Read Only; CoR = Clear on Read Write only; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 174 Description 00 = Normal mode not enter training based on a repeating “11” pattern on RSTAT[1: Train continuously ...
Page 175
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description DIP4_Errors is the total number of DIP4 errors detected since this register was last read. ...
Page 176
... Register Description: Tx and Rx power-down bits to allow per-port power-down of unused ports 31:20 Reserved 19:10 TPWRDWN[9:0] 9:0 RPWRDWN[9: Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 176 Description Reserved Description Reserved Tx power-down for Ports 0 Power-down) Rx power-down for Ports 0 Power-down) ...
Page 177
... R = Read Only; CoR = Clear on Read Write only; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller provide an overview of the Optical Module Interface Block Registers. Description Reserved RX_LOS inputs for Ports 0-9 ...
Page 178
... Reserved 7:0 Read_Data Read Only; CoR = Clear on Read Write only; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 178 Description This bit is set to 1 when a optical module has failed to assert an acknowledge cycle. This signal should be used to validate the data being read. Data is only valid if this bit is equal to zero ...
Page 179
... Ball pitch of 1.0 mm • Overall package dimensions Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Figure 45, “552-Ceramic Ball Grid Array 181): Order Number: 250210, Revision: 009 07-Oct-2005 179 ...
Page 180
... Height of circles surrounding Pb equal to overall character height " does mean a Pin 1 indicator , not an actual mark . Order Number: 250210, Revision: 009 = Intel Product Number = Intel Silicon revision number, A0, A1, B0 … = Pb- Reduced indicator (Same as Jedec) = Intel Finished Process Order (FPO) number = Substrate material number (barely visible) ...
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... Note: All dimensions are in mm. Note: All dimensions are in mm. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (575X) (ø ø (0.91 MAX) (I/O Pads) (0.33 MIN) (Reference) ...
Page 182
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Figure 46. CBGA Package Side View Diagram Note: All dimensions are in mm. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 182 45L4867 (552) Solder ball C4 Encapsulant Fillet Chip 0.81 ± 0.1 (2 ...
Page 183
... N = DIP Q = PQFP H = QFP T = TQFP B = BGA C = CBGA E = TBGA K = HSBGA (BGA with heat slug Product Code xxxxx = 3-5 Digit alphanumeric IXA Product Prefix LXT = PHY layer device IXE = Switching engine IXF = Formatting device (MAC/Framer) IXP = Network processor Intel Package Designator B2577-02 07-Oct-2005 183 ...