HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 90

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
5.6.2.1
07-Oct-2005
90
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Note:
UPX_CS_L
The chip select input when active Low selects IXF1110 MAC for the current cycle. No CPU cycle
is recognized without this signal being active. At the end of the cycle, the chip select can be driven
High to deselect the device or it can be left active if the next access is to the same device (as long as
both Read and Write control signals are inactive between cycles).
The CPU usually supports multiple chip selects, and glue logic is required to drive separate chip
selects if more than one IXF1110 MAC is being controlled by one CPU.
UPX_DATA[31:0]
These pins comprise the 32-bit data bus pins containing data to and from the CPU interface. This
data is asynchronous on the IXF1110 MAC. The Write data provided by the CPU must be stable
during the entire CPU cycle to prevent erroneous Write operations to a register.
UPX_WR_L
This pin indicates there is data on the CPU data bus to be written to the IXF1110 MAC. A Low-to-
High transition latches the data and a High-to-Low transition latches the address. This Write
operation is active Low.
UPX_RD_L
This pin indicates there is data on the CPU data bus to be read from the IXF1110 MAC. A High-to-
Low transition latches the address. This Read operation is active Low.
UPX_RDY_L
This pin indicates the Read or Write cycle is complete for the IXF1110 MAC. This operation is
active Low.
External pull-up resistor required for proper operation.
Read Access
The IXF1110 MAC read access cycle operation is done in the following order:
Figure 24
1. Chip Select (UPX_CS_L) is asserted at all times for the duration of the operation. The address
2. UPX_RD_L should be asserted by the CPU. The IXF1110 latches the address.
3. IXF1110 MAC drives valid data onto the processor bus (UPX_DATA[31:0]).
4. IXF1110 MAC asserts asynchronous-ready (UPX_RDY_L). This indicates to the CPU that the
to be read should be on the IXF1110 MAC address bus (UPX_ADD[10:0]).
Read cycle is complete.
provides the timing of the asynchronous interface for Read access.
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
Datasheet