HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 85

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

5.5.5
Datasheet
Figure 21. Mode 0 Timing
Table 24. Mode 0 Clock Cycle to Data Bit Relationship
Note: Please refer to manufacturers’ 74LS/HC595 datasheet for information on device operation.
When implemented on a board with the M5450 device, the LED DATA bit 1 appears on output bit
3 of the M5450 and the LED DATA bit 2 appears on output bit 4, etc. This means that output bits 1,
2, 3, 34, and 35 will never have valid data and should not be used.
Mode 1: Detailed Operation
The operation of the LED Interface in Mode 1 is again based on a 36-bit counter loop. The data for
each LED is placed in turn on the serial data line and clocked out by the LED_CLK.
Figure 22 on page 86
of each bit.
on the falling edge of the clock and is valid for almost the entire clock cycle. This ensures that the
data is valid during the rising edge of the LED_CLK, which is used to clock the data into the Shift
Register chain devices.
The LED_LATCH signal is required in Mode 1, and is used to latch the data shifted into the shift
register chain into the output latches of the 74HC595 device. As seen in
LED_LATCH signal is active High during the Low period on the 36th LED_CLK cycle. This
avoids any possibility of trying to latch data as it is shifting through the register.
LED_CLK CYCLE
LED_LATCH
LED_DATA
LED_CLK
34:36
4:33
2:3
1
Intel
Figure 22
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
shows the basic timing relationship and relative positioning in the data stream
shows the 36 clocks that are output on the LED_CLK pin. The data changes
1
START BIT
PAD BITS
LED DATA 1-30
PAD BITS
Order Number: 250210, Revision: 009
LED_DATA NAME
2
3
Intel
1
4
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
23 24 25 26 27 28 29 30
26
This bit is used to synchronize the M5450 device to expect 35 bits
of data to follow.
These bits are used only as fillers in the data stream to extend the
length from the actual 30 bit LED DATA to the required 36-bit
frame length. These bits should always be a Logic 0.
These bits are the actual data transmitted to the M5450 device.
The decode for each individual bit in each mode is defined in
Table 23, “LED Signal Descriptions” on page
The data is TRUE. Logic 1(LED ON) = High
These bits are used as fillers in the data stream to extend the
length from the actual 30-bit LED DATA to the required 36-bit
frame length. These bits should always be a Logic 0.
27
28
29
LED_DATA DESCRIPTION
30
31
32
Figure
33
34
22, the
35
84.
36
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