HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 7

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Tables
Datasheet
25 Write Timing – Asynchronous Interface ...................................................................................... 91
26 Power Sequencing......................................................................................................................96
27 Analog Power Supply Filter Network ..........................................................................................97
28 Packet Buffering FIFO ................................................................................................................ 98
29 SFP-to-IXF1110 Connection..................................................................................................... 104
30 CPU Port Read Timing .............................................................................................................110
31 CPU Port Write Timing .............................................................................................................110
32 JTAG Timing............................................................................................................................. 112
33 Transmit Pause Control Interface ............................................................................................. 113
34 Optical Module Interrupt Timing................................................................................................ 114
35 I
36 I
37 Hardware Reset Timing ............................................................................................................ 117
38 LED Timing ............................................................................................................................... 118
39 SerDes Timing .......................................................................................................................... 119
40 SPI4-2 Transmit FIFO Status Bus Timing ................................................................................ 121
41 SPI4-2 Receive FIFO Status Bus Timing ................................................................................. 122
42 Memory Overview..................................................................................................................... 124
43 Register Overview ....................................................................................................................125
44 Markings ................................................................................................................................... 180
45 552-Ceramic Ball Grid Array (CBGA) Package Specifications ................................................. 181
46 CBGA Package Side View Diagram ......................................................................................... 182
47 Ordering Information - Sample ................................................................................................. 183
1
2
3
4
5
6
7
8
9
10
11 Ball List in Alphanumeric Order by Signal Name ........................................................................ 32
12 Ball List in Alphanumeric Order by Ball Location ........................................................................ 38
13 Pause Packets Drop Enable Behavior........................................................................................ 46
14 CRC Errored Packets Drop Enable Behavior ............................................................................. 47
15 Valid Decodes for TXPAUSEADD[3:0] ....................................................................................... 50
16 RMON Additional Statistics Registers ........................................................................................ 55
17 SPI4-2 Interface Signal Summary .............................................................................................. 58
18 Control Word Format .................................................................................................................. 61
19 Control Word Definitions............................................................................................................. 61
20 FIFO Status Format ....................................................................................................................70
21 SerDes Driver TX Power Levels .................................................................................................72
22 IXF1110-to-SFP Connections..................................................................................................... 74
23 LED Signal Descriptions ............................................................................................................. 84
24 Mode 0 Clock Cycle to Data Bit Relationship ............................................................................. 85
SPI4-2 Interface Signal Descriptions ..........................................................................................21
SerDes Interface Signal Descriptions ......................................................................................... 23
CPU Interface Signal Descriptions ............................................................................................. 24
Pause Control Interface Signal Descriptions ..............................................................................25
Optical Module Interface Signal Descriptions ............................................................................. 26
LED Interface Signal Descriptions .............................................................................................. 27
JTAG Interface Signal Descriptions ............................................................................................28
System Interface Signal Descriptions ......................................................................................... 28
2
2
Power Supply Signal Descriptions............................................................................................. 29
Unused Balls/Reserved ............................................................................................................. 31
C Bus Timing.......................................................................................................................... 115
C Write Cycle .........................................................................................................................115
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005
7