HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 76

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
5.4.4
07-Oct-2005
76
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Note:
Note:
Note:
Note:
The MOD_DEF_9:0 inputs shown in
page 177
signal is active to the register bit and/or interrupt being set.
5.4.3.2.6
TX_FAULT_Int is a single output, open-drain type signal, and is active Low. A change in state of
any of the TX_FAULT_9:0 inputs causes this signal to switch Low and remain in this state until a
Read of the
inactive state.
The TX_FAULT_9:0 inputs shown in
page 177
signal is active to the register bit and/or interrupt being set.
5.4.3.2.7
RX_LOS_INT is a single output, open-drain type signal, and is active Low. A change in state of
any of the RX_LOS_0:9 inputs causes this signal to switch Low and remain in this state until a
Read of the Optical Module Status register has taken place. The signal then returns to an inactive
state.
The RX_LOS_0:9 inputs shown in
page 177
signal is active to the register bit and/or interrupt being set.
MOD_DEF_INT, TX_FAULT_INT, and RX_LOS_INT are open-drain type outputs. With the
three signals on the device, the system can decide which Optical module Status Register bits to
look at to identify the interrupt condition source port. However, this is achieved at the expense of
two device pins.
In systems that cannot support multiple interrupt signals (applications that do not have extra
hardware pins), these three outputs can be connected to a single pull-up resistor and used as a
single interrupt pin.
I
The I
SFP multi-source agreement (MSA). This document details the contents of the registers and
addresses accessible on a given optical module supporting this interface.
The SFP MSA identifies up to 512 8-bit registers that are accessible in each optical module. The
I
parameters. The maximum clock rate of the interface is 100 kHz. All address select pins on the
internal E
The specific interface in the IXF1110 supports only a subset of the full I
features required to support the optical modules are implemented, leading to the following support
features:
2
2
C interface is Read/Write capable and supports either sequential or random access to the 8-bit
•
•
C Module Configuration Interface
Single I
Ten per-port I
requirement that all modules must be addressed as 00h.
2
C interface is supported on SFP optical modules. Details of the operation are found in the
are synchronized with an internal system clock. This results in a delay from the time the
are synchronized with an internal system clock. This results in a delay from the time the
are synchronized with an internal system clock. This results in a delay from the time the
2
PROM are tied Low to give a device address equal to zero (00h).
Intel
“Optical Module Status Ports 0-9 ($ 0x799)”
2
C_CLK pin connected to all modules, and implemented to save unnecessary pin use.
Tx_FAULT_INT
RX_LOS_INT
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
2
C_DATA pins optical (I
Order Number: 250210, Revision: 009
Table 108, “Optical Module Status Ports 0-9 ($ 0x799)” on
Table 108, “Optical Module Status Ports 0-9 ($ 0x799)” on
Table 108, “Optical Module Status Ports 0-9 ($ 0x799)” on
2
C_DATA_9:0) are required due to the optical module
takes place. The signal then returns to an
2
C interface, and only the
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