HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 6

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HFIXF1110CC.B2 Q E000

Manufacturer Part Number
HFIXF1110CC.B2 Q E000
Description
Manufacturer
Intel
Datasheet

Specifications of HFIXF1110CC.B2 Q E000

Number Of Transceivers
1
Screening Level
Commercial
Mounting
Surface Mount
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Lead Free Status / RoHS Status
Not Compliant
Intel
8.0
9.0
10.0 Product Ordering Information .................................................................................................. 183
Figures
07-Oct-2005
6
1
2
3
4
5
6
7
8
9
10 Data Path State .......................................................................................................................... 60
11 Per-Port State Diagram with Transitions at Control Words ........................................................ 62
12 DIP-4 Calculation Boundaries .................................................................................................... 63
13 DIP-4 Calculation Algorithm ....................................................................................................... 64
14 FIFO Status State Diagram ........................................................................................................ 68
15 Example of DIP-2 Encoding ...................................................................................................... 69
16 Data Validity Timing.................................................................................................................... 80
17 Start and Stop Definition Timing ................................................................................................. 80
18 Acknowledge Timing .................................................................................................................. 81
19 Random Read ............................................................................................................................ 82
20 Byte Write ................................................................................................................................... 83
21 Mode 0 Timing ............................................................................................................................ 85
22 Mode 1 Timing ............................................................................................................................ 86
23 CPU Interface Inputs/Outputs..................................................................................................... 89
24 Read Timing – Asynchronous Interface ..................................................................................... 91
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Register Definitions................................................................................................................... 123
8.1
8.2
8.3
8.4
8.5
Mechanical Specifications........................................................................................................ 179
9.1
9.2
IXF1110 MAC Block Diagram..................................................................................................... 16
IXF1110 MAC System Block Diagram........................................................................................ 17
552-Ball CBGA Assignments (Top View) ................................................................................... 18
Interface Diagram ....................................................................................................................... 20
Packet Buffering FIFO ................................................................................................................ 48
Ethernet Frame Format .............................................................................................................. 48
PAUSE Frame Format................................................................................................................ 49
Transmit Pause Control Interface ............................................................................................... 51
SPI4-2 Interfacing with the Network Processor or Forwarding Engine....................................... 58
Introduction ....................................................................................................................... 123
Document Structure.......................................................................................................... 123
Graphical Representation ................................................................................................. 123
Per Port Registers ............................................................................................................ 125
Memory Map..................................................................................................................... 125
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
Features............................................................................................................................ 179
IXF1110 MAC Package Specifics..................................................................................... 179
9.2.1
MAC Control Registers ........................................................................................ 133
MAC RX Statistics Register Overview ................................................................. 141
MAC TX Statistics Register Overview ................................................................. 145
Global Status and Configuration Register Overview ........................................... 149
Global RX Block Register Overview .................................................................... 154
TX Block Register Overview ................................................................................ 163
SPI4-2 Block Register Overview.......................................................................... 173
SerDes Register Overview ................................................................................. 175
Optical Module Interface Block Register Overview ............................................. 177
Markings .............................................................................................................. 180
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
Datasheet

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