HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 99

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

6.3.1.2
6.3.1.3
Datasheet
Note: The user must ensure the TX FIFO High and Low Watermarks are programmed correctly to ensure
Note: The TX FIFO drain is enabled using the
The MAC transfer threshold should be set below the
to 9 ($ 0x600 - 0x609)” on page
watermark, the TX FIFO high watermark will act as the MAC transfer threshold. Data is
transmitted out of the TX FIFO to the MAC when the TX FIFO high watermark is reached.
TX FIFO Relation to the SPI4-2 Transmit FIFO Status (TSTAT)
The amount of data in the TX FIFO dictates the FIFO status sent to the NPU on the TSTAT bus.
The following lists how the FIFO status is determined from the TX FIFO High and Low
Watermarks.
SATISFIED: The status given for a port when the amount of data in the per port TX FIFO is greater
than the programmed
HUNGRY: The status given for a port when the amount of data in the per port TX FIFO is between
the programmed
Low Watermark Ports 0 to 9 ($ 0x60A -
STARVING: The status given for a port when the amount of data in the per port TX FIFO is below
the programmed value in
no underrrun or overflow occur. Failure to do this may result in packet loss.
TX FIFO Drain (IXF1110 Version)
The IXF1110 can allow the SPI4-2 NPU or ASIC to dump data to the IXF1110 while the link is
down. This allows the NPU or ASIC to empty its FIFOs, if necessary.
The IXF1110 operates in the following manner under normal operating conditions:
The IXF1110 operates in the following the manner when the TX FIFO drain is enabled:
6.3.1.3.1 Enabling the TX FIFO Drain
The TX FIFO drain is enabled using the
the TX FIFO drain is enabled for a given port:
•
•
•
The TX FIFO is held in reset
The FIFO status for that port indicates SATISFIED
All data sent to that port is discarded
If the IXF1110 detects that the link is down for a given port, the SPI4-2 interface FIFO
status bus indicates SATISFIED. This tells the NPU or ASIC that no data can be passed
across the SPI4-2.
The SPI4-2 FIFO status bus indicates STARVING for the given port. This tells the NPU
or ASIC that it can pass data to the IXF1110 for that port, regardless of the link status, and
all data sent to that port will be discarded.
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
“TX FIFO High Watermark Ports 0 to 9 ($ 0x600 - 0x609)”
“TX FIFO High Watermark Ports 0 to 9 ($ 0x600 -
Order Number: 250210, Revision: 009
“TX FIFO Low Watermark Ports 0 to 9 ($ 0x60A -
163. If the MAC transfer threshold is set above the TX FIFO high
Intel
®
0x613)”.
Section 98, “TX FIFO Drain
“TX FIFO Drain
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Table 94, “TX FIFO High Watermark Ports 0
($0x620)”. The following occurs when
($0x620)”.
0x609)”.
0x613)”.
and the
“TX FIFO
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